EP2S90F1020C5 - Stratix II FPGA 90K LE 1.2V 1020-FBGA | Intel
料号： EP2S90F1020C5 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1750 | $17,500.00 |
| 100 | $1650 | $165,000.00 |
| 500 | $1550 | $775,000.00 |
| 1,000 | $1450 | $1,450,000.00 |
EP2S90F1020C5 概述
Key specifications include 90,960 logic elements (LEs), 4,520,488 total RAM bits distributed across embedded memory blocks, twelve DSP blocks for hardware-accelerated arithmetic, and twelve transceiver-friendly clock PLLs. The device is built on a 1.2 V core supply with multi-voltage I/O support, allowing I/O banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V for mixed-logic interfacing. Maximum internal clock rates exceed 609 MHz per the Stratix II device family datasheet.
This FPGA belongs to the Stratix II family and is one of the highest-density members within the EP2S lineup, sitting above the EP2S60 and below the EP2S130/EP2S180 series. It is fabricated in a 90 nm CMOS process with a 1.2 V core, with eight user I/O banks for flexible mixed-voltage interfacing and dedicated high-speed serial interfaces. The architecture combines adaptive logic modules (ALMs), TriMatrix memory blocks, and DSP blocks to deliver high DSP throughput per watt for bandwidth-intensive designs.
Typical applications include high-speed digital signal processing for wireless baseband, ASIC prototyping, high-performance computing (HPC) emulation platforms, telecommunications line cards, and video/imaging processing pipelines. The Stratix II DSP blocks and large TriMatrix memory make it well suited to FFT, Viterbi, and other compute-intensive algorithms.
When designing with this device, plan for FPGA configuration scheme (fast passive serial, JTAG, or EPC-based controllers), multi-rail decoupling for core and I/O supplies, and adequate PCB thermal relief for the FC-BGA package. Signal integrity work on 1020-ball BGA escape routing and matched-length clock traces is essential to achieve rated performance.
直接替换替代料： EP2S90F1020C5 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EP2S90F1020C5 （相同外形与封装尺寸） ——差异在于 Operating Temperature, Package, Mounting Type, Lead-Free / RoHS, Speed Grade.
快速对比工具——选择替代料号进行并排对比：
EP2S90F1020C4N
✅ 直接替换✓ 有现货
$1320 / 个
查看数据手册 →EP2S90F1020C4
✅ 直接替换✓ 有现货
$1325 / 个
查看数据手册 →EP2S90F1020C3N
✅ 直接替换✓ 有现货
$1995 / 个
查看数据手册 →EP2S90F1020C3
✅ 直接替换✓ 有现货
$640 / 个
查看数据手册 →EP2S90F1020C5 最大额定值与电气特性
| Family | Stratix II |
| Logic Elements | 90,960 |
| Total RAM Bits | 4,520,488 |
| Number of I/O Pins | 758 |
| 电源电压 | 1.15 V to 1.25 V (core) |
| 工作温度 | 0C to +85C (C grade) |
| Package Type | 1020-FBGA (FineLine BGA), 33x33 mm |
| Process Technology | 90 nm CMOS |
| DSP Blocks | 12 (Stratix II DSP) |
| Maximum Operating Frequency | 609.76 MHz |
| 安装类型 | Surface Mount |
| Configuration Mode | Fast Passive Serial / JTAG |
EP2S90F1020C5 1020-fbga (fineline bga), 33x33 mm 引脚配置指南
EP2S90F1020C5（1020-fbga (fineline bga), 33x33 mm 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： EP2S90F1020C5.
请参阅 数据手册 以查看完整引脚配置。
典型应用
EP2S90F1020C5 适用于 6 应用s: ASIC Prototyping Platform, Wireless Baseband Signal Processing, High-Performance Computing Emulation, Telecommunications Line Cards, Video and Imaging Processing Pipelines, Industrial Control and Test Equipment.
ASIC Prototyping Platform
The Intel EP2S90F1020C5 is a strong fit for ASIC prototyping of mid-complexity ASICs (typically 5-8M gates). With 90,960 LEs, 4.5 Mbit TriMatrix memory, and 758 user I/Os, it provides the capacity, embedded memory, and pin count needed to emulate a real ASIC in hardware. The 1020-FBGA 33x33 mm package exposes sufficient user I/O to map most ASIC peripheral interfaces directly to the FPGA without external muxes. Engineers use Quartus II to port ASIC RTL (Verilog/VHDL) to the Stratix II architecture, then validate pre-silicon. Performance is lower than the final ASIC but enables real-world software bring-up, regression testing, and hardware-software co-verification months before silicon is available.
推荐
Wireless Baseband Signal Processing
The EP2S90F1020C5's 12 Stratix II DSP blocks support high-throughput baseband signal processing for wireless systems including LTE, WiMAX, and proprietary OFDM waveforms. Each DSP block contains dedicated multipliers and adders optimized for FFT, Viterbi, and turbo decoding operations. The 4.5 Mbit embedded memory provides intermediate buffering between processing stages, avoiding expensive external memory accesses. With 758 user I/Os, multiple antenna streams and high-speed ADC/DAC interfaces can be connected simultaneously. The C5 speed grade maximizes DSP clock rates to meet throughput requirements, while the 90 nm process delivers competitive power efficiency for telecom line-card deployments.
推荐
High-Performance Computing Emulation
The EP2S90F1020C5 is well-suited for HPC emulation workloads where compute kernels are mapped onto FPGA fabric for hardware acceleration. The 90,960 logic elements and 4.5 Mbit embedded memory handle substantial on-chip data structures, while 758 user I/Os enable PCIe, DDR memory controllers, and high-bandwidth fabric interfaces. HPC workloads in computational genomics, financial Monte Carlo simulation, and machine learning inference benefit from FPGA parallelism. The 1020-FBGA package supports the multi-rail power delivery required for sustained HPC workloads, though careful thermal design is needed because the FC-BGA package concentrates heat. Quartus II supports OpenCL and HLS toolchains for HPC developers.
推荐
Telecommunications Line Cards
Telecom line cards require packet processing, traffic management, and framer functions at line rate, all of which map well onto the EP2S90F1020C5. The 4.5 Mbit TriMatrix memory holds packet descriptors and queue structures, while 758 user I/Os provide SFI/SPI/Interlaken framer interfaces, network processor look-aside connections, and backplane fabric links. The C5 speed grade ensures timing closure at typical telecom clock rates. Multi-voltage I/O bank support (1.5V/1.8V/2.5V/3.3V) lets designers interface to legacy ASICs, FPGAs, and PHYs on the same board. Long-term availability is a concern since the part is obsolete; pair with lifecycle planning.
推荐
Video and Imaging Processing Pipelines
The EP2S90F1020C5 excels at real-time video and image processing pipelines including 4K video codecs, multi-camera stitching, and medical image reconstruction. The 12 DSP blocks deliver pixel-rate FIR filtering, DCT/IDCT transforms, and motion estimation at full video clock rates. 4.5 Mbit embedded memory holds multiple line buffers for spatial-domain processing without external DRAM access for intermediate pixels. 758 user I/Os support HDMI/MIPI/DisplayPort interfaces, camera sensor serializers, and DDR2/DDR3 frame buffers simultaneously. The C5 speed grade maximizes pixel throughput for 4K60 pipelines; lower speed grades may force lower frame rates.
推荐
Industrial Control and Test Equipment
The EP2S90F1020C5 fits industrial test and measurement equipment that needs deterministic real-time processing, custom I/O timing, and flexible interfacing to multiple sensor types. The 758 user I/Os can drive parallel ADCs, DACs, motor encoders, and high-speed serial links from a single device. Logic capacity supports state machines, custom DSP filters, and protocol decoding for industrial buses. The FC-BGA package supports the extended operating temperature range required for industrial deployments. Pair with appropriate voltage regulation and thermal management; obsolete lifecycle status requires long-term inventory planning for production runs.
推荐
推荐产品汇总
工程参考数据： EP2S90F1020C5 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EP2S90F1020C4N | EP2S90F1020C4 | EP2S90F1020C3N | EP2S90F1020C3 |
|---|---|---|---|---|---|
| Package | 1020-FBGA (33x33) | 1020-FBGA (33x33) - same | 1020-FBGA (33x33) - same | 1020-FBGA (33x33) - same | 1020-FBGA (33x33) - same |
| Brand | Intel | Intel - same | Intel - same | Intel - same | Intel - same |
| Family | Stratix II | Stratix II - same | Stratix II - same | Stratix II - same | Stratix II - same |
| Logic Elements | 90,960 | 90,960 - same | 90,960 - same | 90,960 - same | 90,960 - same |
| Total RAM Bits | 4,520,488 | 4,520,488 - same | 4,520,488 - same | 4,520,488 - same | 4,520,488 - same |
| User I/Os | 758 | 758 - same | 758 - same | 758 - same | 758 - same |
| Speed Grade | C5 (fastest) | C4 (slower) | C4 (slower) | C3 (slowest) | C3 (slowest) |
| Core Voltage | 1.2 V (1.15-1.25 V) | 1.2 V - same | 1.2 V - same | 1.2 V - same | 1.2 V - same |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- Highest speed grade (C5) in the EP2S90 family （对比 EP2S90F1020C4)
- Lead-free (Pb-free) C5 variant available for environmental compliance （对比 EP2S90F1020C5 (standard))
- Highest-density Stratix II member in the Site MPN list （对比 EP2S60F1020C5)
设计说明
The Stratix II EP2S90F1020C5 requires a multi-rail power supply: 1.2 V for core logic, plus separate rails for I/O banks (1.5 V, 1.8 V, 2.5 V, or 3.3 V depending on bank configuration), PLL analog supplies, and configuration voltages. Estimated: at full utilization the core may draw 3-5 A; design with at least 20% headroom and use low-impedance decoupling (220 uF bulk plus 0.1 uF / 0.01 uF ceramics per power pin pair). Power sequencing must follow Stratix II datasheet requirements to prevent latch-up.
The 1020-FBGA package concentrates thermal dissipation in a 33x33 mm footprint. Estimated: at full DSP utilization the device can dissipate 8-12 W, requiring thermal vias under the BGA, top-side thermal pads, and possibly a heat sink. Junction-to-ambient thermal resistance depends heavily on PCB copper weight and airflow; design assuming theta_JA around 15-25 C/W with proper thermal management. Use the Stratix II PowerPlay Early Power Estimator to size thermal relief before board layout.
PCB escape routing for a 1020-ball FC-BGA with 1.0 mm ball pitch requires HDI (High Density Interconnect) stack-up with microvias. Use via-in-pad design for BGA escape, signal layers should be dedicated to escape routes, and power/ground planes should be continuous under the BGA. Estimated: a 1020-ball BGA with 4-row escape typically requires 6-8 signal layers plus power/ground planes. Match-length tuning is essential for high-speed DDR2/DDR3 memory interfaces.
Common pitfalls include (1) selecting C4/C3 speed grade by accident when C5 is needed for timing closure, (2) ignoring configuration mode (Fast Passive Serial vs JTAG vs EPC-based) which determines which FPGA configuration device (EPCS or EPC) is required, (3) underestimating power supply ramp requirements which can cause POR (Power-On Reset) failures, and (4) omitting the JTAG chain which is essential for boundary-scan and debug. Always validate the Quartus II fitter report against pin assignments before PCB fabrication.
合规信息
Lifecycle is obsolete. Compliance status not directly extracted from verified web data; engineers should verify RoHS/REACH per date code and N suffix when sourcing for EU/global markets. AEC-Q100 not applicable for FPGA logic devices.
