EP910LC-30 - 24-Macrocell EPLD, 30ns, CMOS PLD | Altera
料号： EP910LC-30 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $39.58 | $39.58 |
| 10 | $35.5 | $355.00 |
| 100 | $30 | $3,000.00 |
| 500 | $26 | $13,000.00 |
| 1,000 | $22.5 | $22,500.00 |
EP910LC-30 概述
An EPLD (Erasable Programmable Logic Device) is a non-volatile PLD technology that combines the architectural simplicity of PAL/GAL devices with erasable CMOS storage cells. In the broader taxonomy, EPLD sits between simple PAL-type devices and higher-density CPLDs/FPGAs - offering LSI-equivalent density with TTL-equivalent speed. EP910-series devices are commonly used as glue-logic replacements for discrete TTL/CMOS gate arrays in control, peripheral, and state-machine applications.
Key features include 24 macrocells with configurable D/T/JK flip-flops, programmable output polarity, on-chip logic test circuitry for production AC verification, and a maximum toggle frequency of approximately 62 MHz. The device supports in-system programming via the Altera MAX+PLUS II development environment, and is available in commercial (LC) and industrial (LI) temperature grades. The 'C' suffix denotes CMOS process, 'L' denotes low-power, and '-30' denotes the 30 ns pin-to-pin propagation delay.
The EP910 architecture uses EPROM-based configuration cells that retain logic when power is removed. Each macrocell contains a programmable AND/OR array, a flip-flop, and an output enable control. The device operates from a single 5 V supply with TTL-compatible I/O. Compared to discrete SSI/MSI logic, a single EP910LC-30 can replace 10-30 standard TTL packages while reducing board area and improving noise immunity.
Typical applications include bus-interface glue logic, address decoding, state-machine control, peripheral interfacing, and prototype ASIC replacement. The device is suitable for industrial control systems, telecom peripheral cards, and instrumentation where deterministic 30 ns timing is acceptable. The PDIP-40 package is preferred for through-hole prototyping, hobbyist designs, and legacy system maintenance.
When designing with this device, allow for the 30 ns propagation delay when calculating setup/hold margins for downstream flip-flops. Use the Altera MAX+PLUS II software for design entry, simulation, and device programming. Decouple the 5 V VCC pin with a 0.1 uF ceramic capacitor placed within 1 cm of the package, and connect all VCC/GND pins.
This page synthesizes distributor pricing, authorized-stock availability through Rochester Electronics, and a drop-in alternatives list (same Altera EP910 family) that DigiKey and Mouser product pages do not aggregate into a single decision-ready view.
直接替换替代料： EP910LC-30 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EP910LC-30 （相同外形与封装尺寸） ——差异在于 Package, Mounting Type, Family, Technology, Programming Method.
快速对比工具——选择替代料号进行并排对比：
EP910LC-25
✅ 直接替换✓ 有现货
$2.2 / 个
查看数据手册 →EP910LC-20
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EP910DC-30
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$15.6 / 个
查看数据手册 →EP910DC-25
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EP910DC-35
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$10.95 / 个
查看数据手册 →EP910DC-40
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$13.95 / 个
查看数据手册 →EP910LC-30 最大额定值与电气特性
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 24 |
| Propagation Delay (tPD) | 30 ns (max) |
| Maximum Toggle Frequency | 62 MHz |
| Supply Voltage (VCC) | 5 V (nominal, TTL) |
| Process Technology | CMOS (EPROM-based) |
| Package Type | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | Commercial (0C to +70C) |
| I/O Pin Count | 24 |
| Dedicated Input Pins | 36 (including I/O) |
| Product Terms per Macrocell | Up to 16 |
| Programming Technology | UV-erasable EPROM cell |
| Development Tool | Altera MAX+PLUS II |
EP910LC-30 引脚配置
| 引脚 1 | I/O — Bidirectional I/O pin (macrocell 0 or input) |
| 引脚 2 | I/O — Bidirectional I/O pin (macrocell 1 or input) |
| 引脚 3 | INPUT — Dedicated input pin |
| 引脚 4 | INPUT — Dedicated input pin |
| 引脚 5 | INPUT — Dedicated input pin |
| 引脚 6 | INPUT — Dedicated input pin |
| 引脚 7 | INPUT — Dedicated input pin |
| 引脚 8 | INPUT — Dedicated input pin |
| 引脚 9 | INPUT — Dedicated input pin |
| 引脚 10 | INPUT — Dedicated input pin |
| 引脚 11 | INPUT — Dedicated input pin |
| 引脚 12 | INPUT — Dedicated input pin |
| 引脚 13 | I/O — Bidirectional I/O pin (macrocell 2 or input) |
| 引脚 14 | I/O — Bidirectional I/O pin (macrocell 3 or input) |
| 引脚 15 | I/O — Bidirectional I/O pin (macrocell 4 or input) |
| 引脚 16 | I/O — Bidirectional I/O pin (macrocell 5 or input) |
| 引脚 17 | I/O — Bidirectional I/O pin (macrocell 6 or input) |
| 引脚 18 | I/O — Bidirectional I/O pin (macrocell 7 or input) |
| 引脚 19 | I/O — Bidirectional I/O pin (macrocell 8 or input) |
| 引脚 20 | I/O — Bidirectional I/O pin (macrocell 9 or input) |
| 引脚 21 | GND — Ground (0 V) |
| 引脚 22 | I/O — Bidirectional I/O pin (macrocell 10 or input) |
| 引脚 23 | I/O — Bidirectional I/O pin (macrocell 11 or input) |
| 引脚 24 | I/O — Bidirectional I/O pin (macrocell 12 or input) |
| 引脚 25 | I/O — Bidirectional I/O pin (macrocell 13 or input) |
| 引脚 26 | I/O — Bidirectional I/O pin (macrocell 14 or input) |
| 引脚 27 | I/O — Bidirectional I/O pin (macrocell 15 or input) |
| 引脚 28 | I/O — Bidirectional I/O pin (macrocell 16 or input) |
| 引脚 29 | I/O — Bidirectional I/O pin (macrocell 17 or input) |
| 引脚 30 | GND — Ground (0 V) |
| 引脚 31 | I/O — Bidirectional I/O pin (macrocell 18 or input) |
| 引脚 32 | I/O — Bidirectional I/O pin (macrocell 19 or input) |
| 引脚 33 | I/O — Bidirectional I/O pin (macrocell 20 or input) |
| 引脚 34 | I/O — Bidirectional I/O pin (macrocell 21 or input) |
| 引脚 35 | I/O — Bidirectional I/O pin (macrocell 22 or input) |
| 引脚 36 | I/O — Bidirectional I/O pin (macrocell 23 or input) |
| 引脚 37 | VCC — +5 V supply |
| 引脚 38 | INPUT — Dedicated input pin (clock/global) |
| 引脚 39 | INPUT — Dedicated input pin (OE/global) |
| 引脚 40 | VCC — +5 V supply |
典型应用
EP910LC-30 适用于 6 应用s: Bus Interface Glue Logic, State Machine Controllers, Address Decoders and Chip Select Generators, Peripheral Interface Adapters, Prototype ASIC Replacement, Legacy Industrial Control Systems.
Bus Interface Glue Logic
The EP910LC-30 is well-suited for legacy ISA/PCI-style bus-interface glue logic, where its 24 macrocells and 36 dedicated inputs can absorb address decoders, chip-select generators, and bus protocol state machines. With a 30 ns propagation delay and 62 MHz maximum toggle frequency, the part meets the timing envelope of 8-bit and 16-bit peripheral buses operating at 8-25 MHz. Designers replace 10-30 discrete TTL/CMOS packages with one EP910LC-30, reducing board area and improving noise immunity. The 5 V TTL-compatible I/O interfaces directly to peripheral controllers without level translation. Recommended companion ICs include the Altera EPM7032AELC44 for higher-density glue logic and the Intel 8255A PPI for parallel I/O expansion. The EP910LC-30 typically sits between the system bus and a peripheral cluster, providing address decoding and handshake sequencing.
推荐
State Machine Controllers
The EP910LC-30 implements multi-state control sequences (Moore/Mealy machines) with up to 24 registered outputs and arbitrary next-state logic. Each macrocell includes a configurable D/T/JK flip-flop with programmable clock polarity, enabling flexible state machine synthesis via AHDL or VHDL in MAX+PLUS II. The 30 ns tPD and 62 MHz fMAX support control loops up to ~16 MHz clock rate with adequate timing margin. Industrial control panels, peripheral card controllers, and instrumentation front-ends all benefit from the deterministic timing of the EP910 architecture. Compared to a discrete HC-series flip-flop implementation, the EP910LC-30 reduces component count by 70% and eliminates timing skew between registers. Recommended companion ICs include the 74HC245 bus transceivers for I/O buffering and the LM555 timer for watchdog reset generation.
推荐
Address Decoders and Chip Select Generators
The EP910LC-30's 24 macrocells and 36 inputs are well-matched to building wide address decoders for 16-bit or 24-bit address buses. The part implements multi-bank memory-mapped I/O decoding with chip-select outputs, replacing 4-8 discrete 74LS138/139 decoder ICs. The 30 ns propagation delay adds negligible latency to memory access cycles, and the EPROM-based configuration retains the decoder map without battery backup. This application is common in single-board computers, embedded controllers, and legacy industrial PCs where the address map is fixed and high reliability is required. Compared to a discrete decoder tree, the EP910LC-30 simplifies PCB routing and improves electromagnetic compatibility. Recommended companion ICs include the 74LS245 transceivers, the HM6116 SRAM, and the Intel 27C256 EPROM for boot storage.
推荐
Peripheral Interface Adapters
The EP910LC-30 connects 8-bit and 16-bit microprocessors (8088, 68000, Z80) to peripheral chips (UARTs, timers, PIOs) by implementing custom register select and handshaking logic. The 24 I/O pins directly drive peripheral chip-select lines and read/write strobes, while the 36 dedicated inputs accept status flags from peripherals. The 30 ns tPD keeps the interface compatible with 8 MHz bus architectures typical of embedded 1980s-1990s designs. The device replaces complex SSI/MSI glue logic that was historically required between the CPU and peripherals, reducing board complexity. Recommended companion ICs include the Zilog Z80 CPU, the Intel 8255A PPI, and the Motorola 68681 DUART. The EP910LC-30 typically sits adjacent to the CPU, providing transparent logic adaptation.
推荐
Prototype ASIC Replacement
Engineers use the EP910LC-30 to prototype small ASIC designs before committing to mask ROM or gate-array fabrication. The EPROM-based configuration is erasable with UV light, allowing iterative logic changes during development. The 24 macrocells are sufficient for 2K-5K gates of equivalent logic, covering typical peripheral controllers, encoder/decoders, and small protocol engines. Once the design stabilizes, the same logic is retargeted to a mask-programmed ASIC or a higher-density CPLD like the EPM7032. The MAX+PLUS II development environment supports schematic, AHDL, and VHDL entry, with functional simulation matching final silicon behavior. Recommended companion ICs include the MAX+PLUS II programming adapter, the Intel iPSC EEPROM for configuration storage, and the Altera ByteBlaster download cable for in-system programming.
推荐
Legacy Industrial Control Systems
The EP910LC-30 maintains operational continuity for installed industrial control systems designed in the 1980s-1990s. Many PLCs, motor controllers, and SCADA RTUs use EP910-family parts as the core sequencing engine, and Rochester Electronics provides factory-traceable replacement stock. The 5 V CMOS operation, 30 ns tPD, and PDIP-40 package allow straightforward board-level repair without redesign. Industrial protocols implemented by the EP910LC-30 include Modbus RTU framing, Profibus token passing, and proprietary fieldbus protocols. The erasable EPROM cells simplify field updates when protocol revisions are required. Recommended companion ICs include the MAX232 RS-232 transceivers, the ADuM1411 digital isolators, and the LM35 temperature sensors for chassis monitoring. The EP910LC-30 typically lives on the controller mainboard, providing deterministic logic that supports decades of field operation.
推荐
推荐产品汇总
工程参考数据： EP910LC-30 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EP910LC-25 | EP910LC-20 | EP910DC-30 | EP910DC-25 | EP910DC-35 | EP910DC-40 |
|---|---|---|---|---|---|---|---|
| Package | PDIP-40 | PDIP-40 (same) | PDIP-40 (same) | CERDIP-40 (through-hole) | CERDIP-40 (through-hole) | CERDIP-40 (through-hole) | CERDIP-40 (through-hole) |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocell Count | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 30 ns | 25 ns (faster) | 20 ns (faster) | 30 ns (same) | 25 ns (faster) | 35 ns (slower) | 40 ns (slower) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial/Military | Industrial/Military | Industrial/Military | Industrial/Military |
| Programming Technology | UV-EPROM | UV-EPROM | UV-EPROM | UV-EPROM | UV-EPROM | UV-EPROM | UV-EPROM |
| Development Tool | MAX+PLUS II | MAX+PLUS II | MAX+PLUS II | MAX+PLUS II | MAX+PLUS II | MAX+PLUS II | MAX+PLUS II |
| Lifecycle Status | Obsolete (Rochester stock) | Obsolete (Rochester stock) | Obsolete (Rochester stock) | Obsolete (Rochester stock) | Obsolete (Rochester stock) | Obsolete (Rochester stock) | Obsolete (Rochester stock) |
关键差异点
- Same-family faster speed grade at no design cost （对比 EP910LC-25)
- Industrial/military temperature grade option （对比 EP910DC-30)
- Modern CPLD alternative with higher density （对比 EPM7032AELC44)
设计说明
The EP910LC-30 requires a single 5 V supply on both VCC pins (37 and 40). Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 1 cm of the package lead, and add a bulk 10 uF tantalum capacitor near the device. The EPLD draws approximately 50-100 mA quiescent current at 25 MHz, scaling with output load and toggle frequency. During EPROM programming, peak current can reach 200 mA - ensure the programmer supplies adequate inrush current. Place a 100 ohm resistor in series with VCC if board-level inrush current is a concern.
Use a 4-layer PCB with continuous ground plane beneath the EP910LC-30 for best signal integrity and EMI suppression. Keep all 12 dedicated inputs and 24 I/O traces short (under 5 cm) and avoid running them parallel to clock signals. Place the MAX+PLUS II programming header (or test pads) at the board edge for easy factory programming. Add a 10 kohm pull-up on the global OE (output enable) input to default outputs to high-impedance during power-up. The PDIP-40 package has sufficient creepage for 5 V digital signals but should not be used in high-voltage or high-humidity environments without conformal coating.
Do not confuse the EP910LC-30 (CMOS commercial, 30 ns, PDIP) with the EP910LI-30 (CMOS industrial, 30 ns, PDIP), EP910DC-30 (CMOS ceramic, 30 ns, CERDIP), or EP910JI-30 (CMOS industrial J-leaded, 30 ns). Each has different temperature grades and package materials. The 'L' suffix means low-power CMOS, 'C' means commercial temperature, 'I' means industrial temperature, 'D' means CERDIP ceramic package, and 'J' means JLCC J-leaded ceramic. Always verify the full ordering code matches your application. Note that the EP910 family is obsolete; consider migrating to EPM7032AELC44 (PLCC-44) or EPM240T100C5N (TQFP-100) for new designs.
The EP910LC-30 outputs have 4 mA drive strength (TTL-compatible), which is sufficient for short PCB traces but inadequate for long cables or backplanes. Add external buffers (74LS245 or 74FCT245) if the design must drive signals more than 15 cm or to multiple loads. Place 33 ohm series termination resistors at the EP910 outputs for traces longer than 5 cm to dampen reflections. The dedicated inputs have TTL-compatible thresholds with 1.4 V VIL and 2.0 V VIH; no Schmitt trigger is provided, so noisy inputs should be filtered externally. The EP910 does not support hot-socketing - ensure clean VCC ramp during power-up.
合规信息
RoHS, REACH, lead-free, and halogen-free status for EP910LC-30 not explicitly stated in verified distributor data. The PDIP-40 commercial part is likely pre-RoHS (original Altera introduction ~1988). For RoHS-compliant EPLDs in modern designs, use EPM7032A or LC4032V series.
