EP910LC-30Y - 24-Macrocell Classic EPLD, 30ns, PLCC-44 | Altera
料号： EP910LC-30Y ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $39.58 | $39.58 |
| 10 | $36.4 | $364.00 |
| 100 | $31.95 | $3,195.00 |
| 500 | $28.1 | $14,050.00 |
| 1,000 | $25.4 | $25,400.00 |
EP910LC-30Y 概述
A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines AND/OR array logic with user-configurable macrocells and output flip-flops. In the broader taxonomy, EPLDs sit between simple PAL/GAL SPLDs and larger CPLDs/FPGAs; they are typically used for glue logic, address decoding, bus interfacing, and state-machine replacement. The EP910LC family specifically targets designs that previously used multiple 20- and 24-pin PAL devices and consolidates them into a single UV-erasable CMOS part with 100% TTL emulation and counter frequencies as high as 100 MHz.
Key features include 24 macrocells (each with a programmable flip-flop and I/O architecture), a 30ns tPD (pin-to-pin delay) at the commercial temperature range, low CMOS standby current, and built-in JTAG/loopback test circuitry that allows verification of function and AC specifications during production flow. The PLCC-44 surface-mount package provides socket compatibility with production programmers and board-test fixtures, and the -LC process variant lowers active supply current compared with the standard EP910. The "Y" suffix indicates an extended-reliability processing flow, often required by defense, aerospace, and long-lifecycle industrial programs.
Architecturally, the EP910LC-30Y uses a sum-of-products PLA structure with a global interconnect and 24 shared expander terms, giving designers enough flexibility to replace several MSI/SSI logic packages with a single in-system programmable device. Programming is performed via standard Altera programming hardware with the MAX+PLUS II development environment, and the device is one-time-programmable (windowless OTP for production, but the UV-erasable ceramic versions allow design iteration).
Typical applications include legacy TTL/CMOS glue-logic consolidation in telecom backplanes, address decoding and wait-state generation in 8086/68k-based embedded systems, industrial PLC and process-control I/O expansion, military and avionics LRUs that need continued support of an Altera Classic part, and FPGA configuration or watchdog logic in mixed-technology boards. The Classic family was historically popular in 1990s-era designs that remain in service or in sustainment programs today.
When designing with this device, ensure the EP910LC-30Y is supplied with a stable 5V ±10% rail and that high-frequency output switching currents are decoupled locally. Designers migrating from older PAL/LSI parts should review the MAX+PLUS II fitter reports, because macrocell feedback paths and expander-term sharing affect achievable fMAX. The PLCC-44 socket footprint simplifies field replacement and programmer-based in-system reconfiguration.
直接替换替代料： EP910LC-30Y ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EP910LC-30Y （相同外形与封装尺寸） ——差异在于 Package, Mounting Type, Supply Voltage (VCC), Operating Temperature, Technology.
快速对比工具——选择替代料号进行并排对比：
EP910LC-30
✅ 直接替换✓ 有现货
$22.5 / 个
查看数据手册 →EP910LC-30T
✅ 直接替换✓ 有现货
$7.1 / 个
查看数据手册 →EP910LC-25
✅ 直接替换✓ 有现货
$2.2 / 个
查看数据手册 →EP910JC-35
✅ 直接替换✓ 有现货
$9.95 / 个
查看数据手册 →EP910JC-30
✅ 直接替换✓ 有现货
$9.75 / 个
查看数据手册 →EP910IPC-25
✅ 直接替换✓ 有现货
$10.4 / 个
查看数据手册 →EP910LC-30Y 最大额定值与电气特性
| Family | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 24 |
| Usable Gates | 450 |
| Pin-to-Pin Delay (tPD) | 30 ns |
| Counter Frequency (fMAX) | 100 MHz (family maximum) |
| 电源电压 | 5 V (TTL-compatible) |
| Process Technology | CMOS, UV-erasable / OTP |
| 封装 | PLCC-44 |
| 工作温度 | Commercial 0C to +70C |
| Speed/Power Grade | LC (low-power, 30ns) |
| Processing Flow | Y (extended reliability) |
| Logic Compatibility | 100% TTL emulation |
| 安装类型 | Surface Mount (PLCC socket) |
EP910LC-30Y 引脚配置
| 引脚 1 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 2 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 3 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 4 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 5 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 6 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 7 | VCC — 5V positive supply |
| 引脚 8 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 9 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 10 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 11 | GND — Ground |
| 引脚 12 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 13 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 14 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 15 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 16 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 17 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 18 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 19 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 20 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 21 | GND — Ground |
| 引脚 22 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 23 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 24 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 25 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 26 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 27 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 28 | VCC — 5V positive supply |
| 引脚 29 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 30 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 31 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 32 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 33 | GND — Ground |
| 引脚 34 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 35 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 36 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 37 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 38 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 39 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 40 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 41 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 42 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 43 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| 引脚 44 | I/O — Bidirectional I/O pin (macrocell-controlled) |
典型应用
EP910LC-30Y 适用于 6 应用s: Legacy TTL/CMOS Glue Logic Consolidation, 8086/68k Address Decoding and Wait-State Generation, Industrial PLC and Process-Control I/O Expansion, Military and Avionics Line-Replaceable Units (LRUs), FPGA Configuration and Watchdog Logic, Telecom Backplane Bus Interface and Arbitration.
Legacy TTL/CMOS Glue Logic Consolidation
The EP910LC-30Y is well suited to consolidate multiple discrete TTL and CMOS logic packages into a single 24-macrocell EPLD in legacy 5V system designs. Its 100% TTL-compatible I/O and 30ns tPD allow direct replacement of 74LS/74F glue-logic functions such as address decoding, bus arbitration, and interrupt steering, while its 450 usable gates comfortably absorb 4-6 SSI/MSI packages. According to Altera's Classic EPLD datasheet, the device operates from a 5V ±10% rail and provides registered macrocell outputs that simplify state-machine replacement in 1990s-era industrial controllers still in service today. Compared with implementing equivalent logic in a modern CPLD, the EP910LC-30Y fits in the same PLCC-44 socket without any PCB rework.
推荐
8086/68k Address Decoding and Wait-State Generation
The EP910LC-30Y is a strong fit for address decoding and wait-state generation in legacy 8086, 68k, and similar microprocessor-based embedded systems. Its 24 macrocells provide enough product terms to decode a full 16-bit address bus with multiple chip-select outputs, while the registered outputs and internal flip-flops can implement wait-state generators and bus-cycle extenders in a single device. According to Rochester Electronics' part record, the EP910 contains 450 usable gates and counter frequencies up to 100 MHz, sufficient to keep pace with 8 MHz and 12 MHz CPU clock domains. The PLCC-44 socket footprint allows in-system programming with Altera's MAX+PLUS II toolchain and ByteBlaster hardware, which many field-service shops still maintain for sustainment programs.
推荐
Industrial PLC and Process-Control I/O Expansion
The EP910LC-30Y continues to be used in industrial PLC and process-control systems as a flexible I/O expander and signal-conditioning glue-logic device. Its extended-reliability Y processing flow supports long-life industrial deployments where component change control is strictly enforced and requalification of new parts would be costly. According to Rochester Electronics' continued-manufacture catalog, the EP910 family is sustained specifically for long-lifecycle industrial and defense customers. The 5V CMOS design tolerates the noisy factory-floor environment, and the 30ns tPD is fast enough to handle deterministic I/O scanning at typical PLC cycle times of 10-50 ms. Designers can implement input-debounce, output-pulse-stretch, and PWM logic directly in macrocells.
推荐
Military and Avionics Line-Replaceable Units (LRUs)
The EP910LC-30Y is widely deployed in military and avionics LRUs as the local glue-logic device on backplane and daughter-card assemblies where reliability and long-term availability are critical. The Y processing flow indicates Altera's extended-reliability screening, and Rochester Electronics' continued-manufacture program guarantees decades of supply for sustainment contracts. According to Altera's Classic datasheet family, the device contains on-board logic test circuitry that allows verification of function and AC specifications during standard production flow, which simplifies factory acceptance testing of avionics subsystems. Its PLCC-44 package is compatible with production programmers and bed-of-nails board-test fixtures used in defense manufacturing.
推荐
FPGA Configuration and Watchdog Logic
The EP910LC-30Y is well suited as a companion device to a main FPGA, providing FPGA configuration memory control, watchdog timer logic, and housekeeping glue in mixed-technology boards. Its 24 macrocells can implement a state machine that sequences FPGA PROG_B, INIT_B, and DONE signals, plus a watchdog timer that resets the FPGA on a stalled configuration handshake. According to the Classic EPLD datasheet, the device supports 100 MHz counter frequencies, fast enough to monitor configuration timeouts on most modern SRAM-based FPGAs. The 5V-tolerant I/O also provides a convenient level-shifting interface between 3.3V FPGAs and 5V backplane logic, although external resistors are recommended for true level translation.
推荐
Telecom Backplane Bus Interface and Arbitration
The EP910LC-30Y is frequently used in telecom backplane assemblies for bus arbitration, interrupt prioritization, and protocol-framing glue logic in legacy T1/E1 and H.110 CT-bus equipment. Its 24 macrocells and 30ns tPD handle the bus-grant propagation delays required for multi-master backplane arbitration, while the 100% TTL-compatible I/O interfaces directly to the 5V backplane transceivers common in 1990s and early-2000s telecom hardware. According to Altera's Classic EPLD family description, the device supports 100% TTL emulation and provides enough logic capacity to implement a complete bus arbiter for 4-6 masters. The PLCC-44 footprint allows socketed field replacement, which is essential for 24/7 telecom installations with strict MTTR budgets.
推荐
推荐产品汇总
工程参考数据： EP910LC-30Y ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EP910LC-30 | EP910LC-30T | EP910LC-25 | EP910JC-35 | EP910JC-30 | EP910IPC-25 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 | 450 |
| Pin-to-Pin Delay (tPD) | 30 ns | 30 ns | 30 ns | 25 ns | 35 ns | 30 ns | 25 ns |
| Processing Flow | Y (extended reliability) | Standard commercial | Standard commercial (tape & reel) | Standard commercial | Standard commercial (ceramic windowed) | Standard commercial (ceramic windowed) | Industrial temp |
| Operating Temperature | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Industrial -40C to +85C |
| Package Type | Plastic Leaded Chip Carrier (PLCC) | Plastic Leaded Chip Carrier (PLCC) | Plastic Leaded Chip Carrier (PLCC) | Plastic Leaded Chip Carrier (PLCC) | Ceramic windowed Leaded Chip Carrier (JLCC) | Ceramic windowed Leaded Chip Carrier (JLCC) | Plastic Leaded Chip Carrier (PLCC) |
| Counter Frequency fMAX (family max) | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
关键差异点
- Extended-reliability Y processing flow for defense and aerospace LRUs （对比 EP910LC-30)
- Identical 30ns tPD to base EP910LC-30 at the same PLCC-44 footprint （对比 EP910LC-25)
- Plastic commercial-grade packaging versus ceramic windowed （对比 EP910JC-30)
设计说明
The EP910LC-30Y operates from a single 5V ±10% supply (4.5V to 5.5V) and its PLCC-44 footprint exposes multiple VCC and GND pins (approximately pins 7, 21, 28, 33 per the family pinout) that must each be decoupled locally. Recommended practice is a 0.1µF ceramic capacitor on every VCC pin placed within 100 mils of the package lead, plus a single 10µF tantalum or aluminum bulk capacitor near the supply entry point. Undecoupled VCC pins in Classic EPLDs cause voltage spikes during simultaneous output switching that can corrupt internal flip-flop states.
Keep I/O traces short and route them away from analog or RF-sensitive areas of the board, because the EP910LC-30Y's TTL outputs generate fast edge rates that couple into adjacent traces. According to Altera's Classic EPLD design guidelines, ground returns should be uninterrupted beneath high-toggle-rate outputs, and the PLCC-44 socket should be soldered to a continuous ground plane when possible. Use 45-degree bends instead of right-angle trace turns to reduce reflections on long (>2 inch) outputs.
A common pitfall when migrating from a PAL or GAL to the EP910LC-30Y is forgetting that macrocell feedback paths and shared expander terms can lower achievable fMAX below the headline 100 MHz figure. According to the MAX+PLUS II fitter output, designs that use heavy expander-term sharing or register-feedback loops typically achieve 60-80 MHz in practice. Always run a timing simulation with the post-fit netlist rather than trusting the family-data fMAX. Also note that the Y suffix is a processing-flow designation and does not change electrical specifications - substituting EP910LC-30 for EP910LC-30Y is acceptable when extended-reliability screening is not required.
合规信息
RoHS, REACH, lead-free, and halogen-free status are not explicitly stated in the verified web data for this Classic EPLD. Rochester Electronics and Altera (Intel) do not publish a current RoHS declaration for the EP910LC-30Y in the retrieved records. AEC-Q100 is not applicable because this is a programmable logic device, not an automotive analog IC. The Y processing flow is Altera's proprietary extended-reliability screening for defense/industrial use.
