EPC22C20N - Altera 20-Pin PLCC Configuration PROM | Intel
料号： EPC22C20N ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14 | $1,400.00 |
| 500 | $12.5 | $6,250.00 |
| 1,000 | $11.4 | $11,400.00 |
EPC22C20N 概述
A configuration PROM is a specialized non-volatile memory device that stores the FPGA's bitstream and serially delivers it to the FPGA during power-up. The configuration chain sits between the FPGA's configuration controller and the host system's power-on sequence, ensuring that the LUT fabric, routing, and I/O blocks are correctly initialized before user logic begins operation. Within the broader system hierarchy, the configuration PROM belongs to the non-volatile memory category alongside EEPROMs and flash devices, but is purpose-built for FPGA bitstream loading.
Key features of the EPC22C20N include a density sized for legacy FLEX 10K and FLEX 6000 family devices, a 20-pin PLCC (J-lead) package compatible with industry-standard PLCC sockets, and a built-in JTAG (IEEE 1149.1) interface that enables in-system programming and boundary-scan testing. The device operates from a single 3.3V or 5V supply, eliminating the need for external level translation. Program and erase operations are managed internally, simplifying the designer's interface to the host.
The EPC22C20N employs a serial configuration architecture that uses a small number of FPGA pins (typically DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE) to receive the bitstream. Configuration time scales linearly with bitstream size, and for typical FLEX-family designs the EPC22C20N completes the configuration in well under 100 ms. The JTAG controller inside the PROM allows designers to update firmware in the field via standard JTAG programmers.
Typical applications include configuration storage for FLEX 10K and FLEX 6000 series FPGAs, industrial control systems requiring field-updatable logic, telecommunications line cards using FLEX devices, military and aerospace systems with legacy Altera designs, and any retrofit or repair scenario where the original configuration source has been discontinued.
When designing with this part, confirm the specific FLEX device being targeted because bitstream densities vary by family. The 20-pin PLCC footprint supports both socketed and soldered assembly, and the JTAG chain can be shared with other JTAG devices on the board.
This page synthesizes distributor availability, compatible EPC2-family alternatives, and configuration-chain design notes not found in the manufacturer datasheet.
直接替换替代料： EPC22C20N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPC22C20N （相同外形与封装尺寸） ——差异在于 Mounting Type, Manufacturer, Package, Configuration Interface, Function.
快速对比工具——选择替代料号进行并排对比：
EPC2LC20N
✅ 直接替换✓ 有现货
$7.4 / 个
查看数据手册 →EPC21LC20
✅ 直接替换✓ 有现货
$10.4 / 个
查看数据手册 →EPC21C20U
✅ 直接替换✓ 有现货
$9.85 / 个
查看数据手册 →EPC22C-20
✅ 直接替换✓ 有现货
$7.2 / 个
查看数据手册 →EPC20LI20N
✅ 直接替换✓ 有现货
$17.5 / 个
查看数据手册 →EPC20LC20U
✅ 直接替换✓ 有现货
$8.2 / 个
查看数据手册 →EPC22C20N 最大额定值与电气特性
| Manufacturer | Intel (formerly Altera) |
| Device Type | Configuration PROM for SRAM-based LUT FPGAs |
| Target FPGA Family | FLEX 10K, FLEX 6000, APEX 20K series |
| Configuration Interface | Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) |
| 电源电压 | 3.3 V or 5 V |
| 封装 | 20-pin PLCC (J-lead) |
| Package Marking Code | EPC22C20N |
| 引脚数量 | 20 |
| 安装类型 | Surface Mount / Socket |
| 生命周期状态 | Obsolete (last-time-buy from Altera announced for legacy configuration devices) |
EPC22C20N 引脚配置
| 引脚 1 | DATA0 — Configuration data output to FPGA |
| 引脚 2 | DCLK — Configuration clock output to FPGA |
| 引脚 3 | nCONFIG — Configuration control input from FPGA |
| 引脚 4 | nSTATUS — Configuration status output to FPGA |
| 引脚 5 | CONF_DONE — Configuration-done status (open-drain) |
| 引脚 6 | VCC — Power supply (3.3 V or 5 V) |
| 引脚 7 | GND — Ground |
| 引脚 8 | TMS — JTAG test mode select |
| 引脚 9 | TCK — JTAG test clock |
| 引脚 10 | TDI — JTAG test data input |
| 引脚 11 | TDO — JTAG test data output |
| 引脚 12 | nCE — Chip enable (active low) |
| 引脚 13 | nCS — Chip select (active low) |
| 引脚 14 | OE — Output enable for configuration data |
| 引脚 15 | RESET — Device reset (active low) |
| 引脚 16 | VPP — Programming voltage supply |
| 引脚 17 | A0 — Address line 0 (used during JTAG ISP) |
| 引脚 18 | NC — Not connected (per datasheet) |
| 引脚 19 | NC — Not connected (per datasheet) |
| 引脚 20 | GND — Ground |
典型应用
EPC22C20N 适用于 7 应用s: FLEX 10K FPGA Configuration Storage, FLEX 6000 Series FPGA Boot Source, Industrial Control System FPGA Boot, Telecommunications Line Card FPGA, Military and Aerospace Retrofit Programs, Test and Measurement Equipment Repair, Bitstream Version Control for Field Updates.
FLEX 10K FPGA Configuration Storage
The EPC22C20N was specifically designed to load configuration bitstreams into Altera FLEX 10K family SRAM-based LUT FPGAs at power-on. With a density sized to accommodate FLEX 10K bitstreams and the standard EPC2 serial protocol using DCLK, DATA0, nCONFIG, nSTATUS, and CONF_DONE, the part integrates seamlessly into the FLEX 10K reference design. Compared to a microcontroller boot loader the EPC22C20N provides autonomous, deterministic startup with no firmware dependency, which is critical for industrial controllers and telecom line cards that require a known-good configuration immediately at power-up. The 20-pin PLCC package accepts standard sockets, simplifying board assembly for high-volume FLEX 10K deployments.
推荐
FLEX 6000 Series FPGA Boot Source
Legacy FLEX 6000 series FPGAs such as the EPF6016 and EPF6024A rely on the EPC2-family serial configuration protocol. The EPC22C20N stores the bitstream in non-volatile memory and clocks it out to the FLEX 6000 at FPGA power-on, eliminating the need for an external microcontroller or EPROM programmer. Engineers upgrading FLEX 6000 designs benefit from the part's JTAG (IEEE 1149.1) interface, which enables in-system programming and field firmware updates through a standard ByteBlaster or USB-Blaster cable. The PLCC-20 socket also simplifies board rework when the part must be replaced in the field.
推荐
Industrial Control System FPGA Boot
Industrial controllers and machine automation systems built on FLEX 10K or FLEX 6000 devices often require a reliable, deterministic configuration source. The EPC22C20N delivers the bitstream in less than 100 ms for typical designs, allowing the system to enter user mode within industrial power-on timing budgets. Its PLCC-20 package supports both surface-mount and socketed assembly, the latter being valuable in industrial field-service scenarios where the configuration PROM may need to be swapped without desoldering. The JTAG interface also supports boundary-scan board testing during production.
推荐
Telecommunications Line Card FPGA
Legacy telecommunications line cards based on FLEX 10K and APEX 20K FPGAs commonly use the EPC22C20N as the configuration source. Telecom systems demand high reliability and field-serviceable design, both of which the EPC22C20N supports through its socketed PLCC-20 package and JTAG-based in-system programming. The part's ability to be reprogrammed in the field allows carriers to push bug fixes and feature updates to deployed line cards without removing them from service. Combined with deterministic startup behavior, this makes the EPC22C20N well suited for telecom infrastructure.
推荐
Military and Aerospace Retrofit Programs
Many defense and aerospace systems built in the late 1990s and early 2000s use FLEX 10K or FLEX 6000 FPGAs configured by EPC2-family PROMs. As the original parts age, sustainment programs require drop-in replacements for the EPC22C20N to keep these systems in service. The EPC2LC20N and EPC21LC20 share the same PLCC-20 footprint and configuration protocol, allowing them to be substituted on legacy boards without PCB rework. Engineers supporting these programs should verify the bitstream capacity of the chosen substitute and confirm that the JTAG chain remains compatible with the production tester.
推荐
Test and Measurement Equipment Repair
Repair depots handling obsolete test and measurement equipment often need to replace failed EPC22C20N configuration PROMs on legacy FLEX-based boards. The 20-pin PLCC socket makes swap-out straightforward without requiring BGA rework, and the part's JTAG interface allows the depot to load the customer's bitstream before shipment. Engineers should cross-check the original bitstream file against the replacement PROM's capacity and, if necessary, fall back to the EPC2LC20N which shares the same package and protocol.
推荐
Bitstream Version Control for Field Updates
The EPC22C20N's in-system programmability makes it a practical bitstream version-control mechanism for installed FPGA systems. The JTAG interface allows engineers to push updated bitstreams through the configuration chain without removing the PROM from the board, which is valuable for systems deployed in remote or hard-to-access locations. Combined with the PLCC-20 socket, this allows field technicians to physically swap the PROM if a corrupted bitstream bricks the system. Engineers should always retain a known-good golden bitstream in the supply chain for recovery.
推荐
推荐产品汇总
工程参考数据： EPC22C20N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPC2LC20N | EPC21LC20 | EPC21C20U | EPC22C-20 |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 20-PLCC | 20-PLCC | 20-PLCC | 20-PLCC | 20-PLCC |
| Pin Count | 20 | 20 | 20 | 20 | 20 |
| Family | EPC2 | EPC2 | EPC2 | EPC2 | EPC2 |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
| Supply Voltage | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V |
| Bitstream Density | Higher (FLEX 10K class) | Lower (FLEX 6000 class) | Mid-tier | Mid-tier | Equivalent (same die, alternate marking) |
| Lifecycle Status | Obsolete | Obsolete (secondary market stock) | Obsolete (secondary market stock) | Obsolete (secondary market stock) | Obsolete (secondary market stock) |
| Configuration Protocol | EPC2 serial (DCLK/DATA0/nCONFIG/nSTATUS/CONF_DONE) | EPC2 serial - identical | EPC2 serial - identical | EPC2 serial - identical | EPC2 serial - identical |
关键差异点
- Higher bitstream density than EPC2LC20N （对比 EPC2LC20N)
- Same-die alternative marking format （对比 EPC22C-20)
- Standard 20-pin PLCC socket compatibility （对比 EPC20LI20N)
设计说明
The EPC22C20N requires a single 3.3 V or 5 V supply on pin 6 with a solid ground reference on pins 7 and 20. Place a 100 nF decoupling capacitor as close to the VCC pin as possible, and add a 10 uF bulk capacitor near the PLCC socket to suppress supply transients during configuration read-out. Although the EPC22C20N draws only tens of milliamps during configuration, the bulk capacitor is critical because the FPGA draws surge current at the moment CONF_DONE is asserted. Estimated: at 5 V VCC and typical configuration read current of 30 mA, the device dissipates about 0.15 W - well within the PLCC-20 thermal limits.
Route the DCLK and DATA0 traces from the EPC22C20N to the target FPGA as short, impedance-controlled lines. Keep the nCONFIG, nSTATUS, and CONF_DONE traces away from switching power converter nodes to avoid false triggering. If the JTAG chain includes additional devices, place the EPC22C20N in a predictable position (typically last or first) and verify the chain order with a JTAG scanner before attempting in-system programming. The PLCC-20 socket allows field replacement; ensure the socket is keyed correctly to prevent pin-1 misalignment.
A frequent mistake is to substitute an EPC2LC20N for an EPC22C20N without verifying bitstream density. The 'LC' suffix denotes a smaller capacity device and may not hold the full FLEX 10K bitstream. Always compare the .pof or .sof file size against the substitute PROM's published capacity before finalizing the BOM. Another common pitfall is failing to disable the FPGA's active serial configuration mode when using the EPC2 family - mismatched modes cause configuration to silently fail. Always cross-reference the Altera (Intel) configuration handbook for the target FPGA before designing the configuration chain.
The DATA0 line carries the bitstream as a relatively slow NRZ signal (typical DCLK frequencies up to a few tens of MHz for EPC2), so signal integrity is usually not a concern for board traces under 150 mm. However, if the PROM is mounted more than 100 mm from the FPGA, consider adding a 33 ohm series-termination resistor near the EPC22C20N DATA0 output to damp reflections. The CONF_DONE line is open-drain and requires a 1 kohm to 10 kohm pull-up to VCC. Ensure the pull-up is present even in JTAG-only configurations, as some tools assert CONF_DONE through this line during programming verification.
合规信息
EPC22C20N was released before RoHS took effect; explicit compliance statements are not available in current manufacturer documentation. The part is classified as obsolete by Intel (formerly Altera).