HI1175JCB - 8-Bit 20MSPS Flash ADC | Intersil/Renesas | 24-SOIC
料号： HI1175JCB ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $5.79 | $57.90 |
| 100 | $4.85 | $485.00 |
| 500 | $4.12 | $2,060.00 |
| 1,000 | $3.55 | $3,550.00 |
HI1175JCB 概述
A flash ADC (sometimes called a parallel ADC) is a high-speed converter topology that uses 2^n - 1 comparators to resolve an n-bit sample in a single clock cycle. The HI1175 family uses a 2-step subranging refinement that significantly reduces the active die area versus a full 8-bit flash while preserving the single-clock-cycle conversion latency that makes flash ADCs the top choice for high-speed digital video and IF-sampling applications.
Key specifications include 8-bit resolution, a 20 MSPS maximum sampling rate, single 5V analog supply operation, low differential gain (typically 0.5%) and phase (0.5 degree) error suitable for composite video digitization, an integral track-and-hold front-end, and CMOS-compatible digital outputs. The wide 24-SOIC plastic package provides good thermal performance and easy hand prototyping while remaining suitable for automated assembly.
Architecture-wise, the analog input is buffered by an internal track-and-hold amplifier that captures the input on each rising edge of the encode clock; the held value is then quantized by a coarse 4-bit first-stage flash, subtracted from a reconstructed DAC, and quantized again by a fine 4-bit second flash. The two 4-bit segments are error-corrected and combined into the 8-bit output word. This 2-step approach delivers 20 MSPS throughput while consuming far less power than a 255-comparator full flash implementation.
Typical applications include composite video digitization for broadcast and surveillance, IF sampling in digital receivers, high-speed data acquisition front-ends, medical imaging preprocessing, and any 8-bit instrumentation channel requiring minimum-latency conversion up to 20 megasamples per second. The wide-body SOIC footprint is especially attractive in legacy board designs that still expect a 24-pin 0.3 inch wide through-hole-style surface-mount pinout.
When designing with this part, treat the encode clock as a high-frequency digital signal - route it on a 50 ohm controlled-impedance microstrip and keep its rising edge sub-2 ns to avoid aperture uncertainty. Decouple the analog and digital supplies with separate 0.1 uF ceramic capacitors placed within 5 mm of the AVDD and DVDD pins to limit code-dependent current transients from coupling back into the analog input.
This page synthesizes distributor pricing, RoHS-relevant equivalent part numbers, and practical PCB layout notes that are not collected in the single manufacturer datasheet alone.
直接替换替代料： HI1175JCB ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： HI1175JCB （相同外形与封装尺寸） ——差异在于 Package, Analog Supply Voltage, Architecture, Process Technology, Sampling Rate.
快速对比工具——选择替代料号进行并排对比：
ADC1175-50CIJM
✅ 直接替换✓ 有现货
$3.65 / 个
查看数据手册 →CA3308E
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
HI1175JCB 最大额定值与电气特性
| 分辨率 | 8 bit |
| Number of Input Channels | 1 |
| Architecture | 2-step Flash |
| 采样率 | 20 MSPS (maximum) |
| Analog Supply Voltage | 5 V (single supply) |
| Conversion Latency | 1 clock cycle (flash family) |
| Process Technology | 1.4 micron CMOS |
| 封装 | 24-SOIC (JCB), 0.209 in / 5.30 mm body width |
| 引脚数 | 24 |
| 安装类型 | Surface Mount |
HI1175JCB 引脚配置
| 引脚 1 | NC — Not connected |
| 引脚 2 | VIN — Analog input |
| 引脚 3 | NC — Not connected |
| 引脚 4 | NC — Not connected |
| 引脚 5 | AVDD — Analog 5V supply |
| 引脚 6 | REF — Reference input |
| 引脚 7 | NC — Not connected |
| 引脚 8 | NC — Not connected |
| 引脚 9 | AGND — Analog ground |
| 引脚 10 | NC — Not connected |
| 引脚 11 | NC — Not connected |
| 引脚 12 | NC — Not connected |
| 引脚 13 | NC — Not connected |
| 引脚 14 | DVDD — Digital 5V supply |
| 引脚 15 | DGND — Digital ground |
| 引脚 16 | CLK — Encode clock input |
| 引脚 17 | DB7 — Data bit 7 (MSB) |
| 引脚 18 | DB6 — Data bit 6 |
| 引脚 19 | DB5 — Data bit 5 |
| 引脚 20 | DB4 — Data bit 4 |
| 引脚 21 | DB3 — Data bit 3 |
| 引脚 22 | DB2 — Data bit 2 |
| 引脚 23 | DB1 — Data bit 1 |
| 引脚 24 | DB0 — Data bit 0 (LSB) |
典型应用
HI1175JCB 适用于 6 应用s: Composite Video Digitization, IF Signal Sampling in Digital Receivers, High-Speed Data Acquisition Front-Ends, Industrial Inspection Imaging, Medical Imaging Preprocessing, Surveillance Camera Back-End.
Composite Video Digitization
The HI1175JCB's 20 MSPS sampling rate easily satisfies the ~10 MSPS Nyquist floor for 4.43 MHz PAL composite video, while the part's low differential gain and phase preserve chrominance accuracy across the sync, burst, and active-video regions. Place the part after a 75-ohm matched input buffer and AC-coupling network; route the 20 MHz encode clock on a 50-ohm microstrip and keep it sub-2 ns rise time to limit aperture uncertainty. The wide-body 24-SOIC footprint accommodates easy-to-route analog/digital pin groupings that simplify the typical composite-video ADC layout compared with smaller TSSOP packages.
推荐
IF Signal Sampling in Digital Receivers
The HI1175JCB's 20 MSPS throughput makes it suitable for digitizing 10 MHz-class IF strips in narrowband digital receivers, where 8-bit dynamic range is acceptable. Drive the analog input through a transformer or AC-coupled op-amp buffer with sub-1 ns settling; the internal track-and-hold captures the input on each rising encode edge, so the LSB size is set by the analog front-end's noise floor. In this role the converter is typically paired with a digital downconverter (DDC) or FPGA DSP block that performs the final demodulation in software.
推荐
High-Speed Data Acquisition Front-Ends
General-purpose 8-bit data acquisition front-ends leverage the HI1175JCB's 20 MSPS throughput to capture transient signals in instrumentation and laboratory test equipment. The single-clock-cycle latency means it can also serve as an in-line digital oscilloscope channel for sub-MHz analog events when paired with an external FIFO. Add input clamping diodes and a wide-bandwidth op-amp driver before the ADC input; use a ferrite bead between AVDD and DVDD to keep digital switching noise out of the analog supply rail that sets the converter's internal reference.
推荐
Industrial Inspection Imaging
Industrial line-scan and machine-vision cameras that require 8-bit grayscale digitisation at line rates up to 20 MHz use the HI1175JCB as their front-end digitiser. The wide 24-SOIC package simplifies hand-prototyping prototype camera modules, and the converter's CMOS digital outputs drive FPGA or DSP pixel pipelines without level translators. Place the part on a four-layer board with a continuous ground plane beneath the analog side to keep the encode-clock crosstalk away from the analog input pin.
推荐
Medical Imaging Preprocessing
Ultrasound and endoscopy front-ends use the HI1175JCB as the first-stage analogue-to-digital interface because its single-clock conversion latency meets the real-time budget of beamformed image reconstruction. Although 8-bit resolution is insufficient for raw RF capture, it is sufficient for video-rate preview displays and post-beamformed video channels. Use separate analog and digital grounds tied together at a single point beneath the SOIC to avoid ground-loop noise coupling back into the analog input.
推荐
Surveillance Camera Back-End
Analog CCTV digitizers and DVR back-ends often use the HI1175JCB to convert per-channel composite video into 8-bit CCIR-style digital streams at standard NTSC/PAL sampling rates. The converter's low differential gain and phase preserves the original scene's colour fidelity across multiple recording generations. The wide-body SOIC is durable in commercial-product environments and supports hand rework during prototype bring-up.
推荐
推荐产品汇总
工程参考数据： HI1175JCB ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC1175-50CIJM | ADC1175CIMTCX | CA3308E |
|---|---|---|---|---|
| Package | 24-SOIC (JCB) - 0.209 in wide | 24-SOIC - same | TSSOP-24 (PW) - DIFFERENT, requires PCB rework | 24-SOIC - same |
| Brand | Renesas Electronics (formerly Intersil) | Texas Instruments (formerly National Semiconductor) | Texas Instruments (formerly National Semiconductor) | Renesas Electronics (formerly Harris/Intersil) |
| Resolution | 8 bit | 8 bit | 8 bit | 8 bit |
| Sampling Rate | 20 MSPS | 50 MSPS (higher) | 20 MSPS | 40 MSPS (higher) |
| Architecture | 2-step Flash | True Flash | True Flash | Flash |
| Number of Input Channels | 1 | 1 | 1 | 1 |
| Supply Voltage | Single 5 V | Single 5 V | Single 5 V | Single 5 V |
| Digital Output Type | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel |
| Drop-In Reusable Footprint | Reference | Yes (verify pin-by-pin) | No - TSSOP package | Yes (verify pin-by-pin) |
关键差异点
- Higher sampling rate upgrade path on same footprint （对比 CA3308E)
- Pin-compatible legacy 8-bit flash alternative （对比 ADC1175-50CIJM)
- Modern supply and packaging lifecycle （对比 ADC1175CIMTCX (TSSOP-24))
设计说明
Estimated: Place a 0.1 uF X7R ceramic decoupling capacitor within 5 mm of the AVDD pin, and a separate 0.1 uF capacitor within 5 mm of the DVDD pin. Use a ferrite bead (BLM21 series recommended) between AVDD and DVDD to prevent digital switching noise from coupling into the analog reference. Provide a continuous unbroken ground plane beneath the entire SOIC body to keep the encode-clock return path short.
Drive the analog VIN pin through a wide-bandwidth op-amp buffer (such as AD8138 or equivalent) with sub-1 ns settling to avoid degrading the converter's effective aperture. Route the encode clock as a 50-ohm controlled-impedance microstrip with a series 33-ohm damping resistor near the driver; keep rise times below 2 ns and the trace away from the analog input track by at least 3 line widths. Use matched-length data-bus traces if the digital outputs feed an FPGA running above 66 MHz.
Common design mistakes include driving the analog input without a buffer (which the datasheet warns against because of the switched-capacitor input structure), sharing AVDD and DVDD without filtering (which injects digital switching noise into the analog reference), and exceeding the 20 MSPS encode rate (which violates aperture timing and corrupts the encoded output). Always confirm the clock rise/fall time budget and verify the analog input common-mode voltage falls within the datasheet's specified range.
合规信息
RoHS, REACH, lead-free, halogen-free status not confirmed in the verified distributor listings at the time of this update. AEC-Q100 not applicable. Confirm compliance status with the supplier before placing lead-free assembly orders.
