HI5762/6IN - Dual 10-Bit 60MSPS ADC, 44-MQFP | Renesas
料号： HI5762/6IN ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
HI5762/6IN 概述
What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage converter architecture that uses several low-resolution flash stages connected in series, with each stage sampling and converting a coarse slice of the input before passing the residue to the next stage. Compared to successive-approximation (SAR) or simple flash converters, pipelined ADCs deliver the highest sample rates (tens to hundreds of MSPS) at moderate resolution, making them the workhorse of digitizing wideband intermediate-frequency (IF) signals, video, and baseband communications. The HI5762/6IN is part of the broader analog-to-digital converter product hierarchy (ADC → pipelined ADC → high-speed CMOS ADC → data acquisition IC).
Key features include dual 10-bit resolution, 60 MSPS maximum sample rate per channel, CMOS-compatible digital outputs, an internal voltage reference (eliminating the need for an external reference and saving PCB area), low power consumption typical of CMOS ADC designs, and built-in analog input clamping. The two converters share a common reference but have independent analog inputs, clock inputs, and digital output buses, allowing simultaneous sampling of two signals.
Architecturally, the HI5762/6IN combines two cores of the HI5767 single-channel 10-bit 60 MSPS ADC, sharing only the on-chip bandgap reference and common supply pins. This level of integration reduces board area, lowers system cost, and improves channel-to-channel matching versus a discrete two-ADC solution. The advanced CMOS process contributes to low power dissipation and high digital integration density.
Typical applications include high-speed data acquisition systems, medical imaging front-ends, IF sampling in communications receivers, professional video digitizers, and test-and-measurement instrumentation such as digital oscilloscopes and arbitrary waveform digitizers. The dual-channel nature is particularly suited to I/Q baseband sampling, diversity receiver paths, and dual-antenna or phased-array signal capture.
When designing with the HI5762/6IN, pay particular attention to clock jitter: the analog input bandwidth and 60 MSPS sample rate require a low-jitter (sub-ps) clock source to preserve SNR. Ensure analog inputs are AC-coupled or properly biased within the common-mode input range, and place the internal reference bypass capacitor as recommended in the datasheet to minimize digital-noise feed-through.
This page synthesizes Renesas datasheet parameters, current distributor pricing, drop-in compatible alternatives, and PCB-layout guidance not found in a single OEM source.
直接替换替代料： HI5762/6IN ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： HI5762/6IN （相同外形与封装尺寸） ——差异在于 Architecture, Number of Channels, Resolution, Input Type, Package Type.
快速对比工具——选择替代料号进行并排对比：
HI5762/6IAZ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
HI5762/6CN
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
HI5762/6IN 最大额定值与电气特性
| Architecture | Dual pipelined 10-bit ADC |
| Number of Channels | 2 |
| 分辨率 | 10 bit |
| Sample Rate | 60 MSPS (per channel) |
| Input Type | Differential/Single-ended analog |
| Digital Output Interface | Parallel CMOS |
| Internal Voltage Reference | Yes (on-chip) |
| Package Type | MQFP-44 (44-MQFP) |
| 引脚数量 | 44 |
| Process Technology | Advanced CMOS |
HI5762/6IN 引脚配置
| 引脚 1 | DA9 — Channel A digital output bit 9 (MSB) |
| 引脚 2 | DA8 — Channel A digital output bit 8 |
| 引脚 3 | DA7 — Channel A digital output bit 7 |
| 引脚 4 | DA6 — Channel A digital output bit 6 |
| 引脚 5 | DA5 — Channel A digital output bit 5 |
| 引脚 6 | DA4 — Channel A digital output bit 4 |
| 引脚 7 | DA3 — Channel A digital output bit 3 |
| 引脚 8 | DA2 — Channel A digital output bit 2 |
| 引脚 9 | DA1 — Channel A digital output bit 1 |
| 引脚 10 | DA0 — Channel A digital output bit 0 (LSB) |
| 引脚 11 | DVDD — Digital supply |
| 引脚 12 | DGND — Digital ground |
| 引脚 13 | DB0 — Channel B digital output bit 0 (LSB) |
| 引脚 14 | DB1 — Channel B digital output bit 1 |
| 引脚 15 | DB2 — Channel B digital output bit 2 |
| 引脚 16 | DB3 — Channel B digital output bit 3 |
| 引脚 17 | DB4 — Channel B digital output bit 4 |
| 引脚 18 | DB5 — Channel B digital output bit 5 |
| 引脚 19 | DB6 — Channel B digital output bit 6 |
| 引脚 20 | DB7 — Channel B digital output bit 7 |
| 引脚 21 | DB8 — Channel B digital output bit 8 |
| 引脚 22 | DB9 — Channel B digital output bit 9 (MSB) |
| 引脚 23 | DGND — Digital ground |
| 引脚 24 | CLK_B — Channel B sample clock input |
| 引脚 25 | AVDD — Analog supply |
| 引脚 26 | AGND — Analog ground |
| 引脚 27 | AIN_B — Channel B analog input |
| 引脚 28 | VREF — Internal voltage reference output / bypass |
| 引脚 29 | AGND — Analog ground |
| 引脚 30 | AVDD — Analog supply |
| 引脚 31 | AIN_A — Channel A analog input |
| 引脚 32 | AGND — Analog ground |
| 引脚 33 | CLK_A — Channel A sample clock input |
| 引脚 34 | NC — Not connected (per datasheet) |
| 引脚 35 | NC — Not connected (per datasheet) |
| 引脚 36 | NC — Not connected (per datasheet) |
| 引脚 37 | AGND — Analog ground |
| 引脚 38 | AVDD — Analog supply |
| 引脚 39 | AGND — Analog ground |
| 引脚 40 | AVDD — Analog supply |
| 引脚 41 | DVDD — Digital supply |
| 引脚 42 | DGND — Digital ground |
| 引脚 43 | DVDD — Digital supply |
| 引脚 44 | DGND — Digital ground |
典型应用
HI5762/6IN 适用于 6 应用s: Dual-Channel Data Acquisition Systems, Medical Imaging Front-End, Communications IF Sampling, Professional Video Digitizing, Industrial Test & Measurement, Radar and Phased Array Digitizers.
Dual-Channel Data Acquisition Systems
The HI5762/6IN's dual 10-bit 60 MSPS pipelined architecture captures two simultaneous high-speed analog signals in a single 44-MQFP IC, eliminating the cost and channel-matching drift of two discrete ADCs. Each channel samples at up to 60 MSPS with parallel CMOS outputs, reducing downstream FPGA/ASIC capture complexity. The integrated reference simplifies PCB layout and improves thermal coupling between channels, while advanced CMOS fabrication keeps power dissipation manageable for sealed industrial chassis.
推荐
Medical Imaging Front-End
The HI5762/6IN supports ultrasound, MRI receiver arrays, and other medical-imaging front-ends where two channels of baseband or IF data must be digitized concurrently. Its 60 MSPS per-channel rate, internal voltage reference, and small MQFP-44 footprint reduce PCB area in portable imaging carts. Pair with a sub-picosecond clock source to maximize SNR at the narrow analog-input bandwidths typical of medical RF chains.
推荐
Communications IF Sampling
With 60 MSPS per channel, the HI5762/6IN is well suited to IF sampling in cellular base-station receivers, software-defined radio (SDR) boards, and diversity receiver paths that require I/Q digitization. The dual-channel nature permits concurrent I and Q sampling on a shared clock reference. The CMOS output bus interfaces cleanly to modern FPGAs implementing digital down-conversion, and the integrated voltage reference eliminates the external LDO+bandpass combination typically required at IF frequencies.
推荐
Professional Video Digitizing
The HI5762/6IN's dual simultaneous 10-bit sampling at 60 MSPS supports component video digitizers, broadcast-quality capture cards, and studio cameras. Two channels cover Y/C separation or a Y/R-Y/B-Y triplet when paired with external muxing, while the parallel CMOS outputs minimize latency compared to serialized LVDS solutions. The internal reference stabilizes black-level calibration across broadcast temperature environments.
推荐
Industrial Test & Measurement
The dual channels allow two input ranges or two probe channels to be captured at 60 MSPS in test-and-measurement instruments such as digital oscilloscopes, spectrum analyzers, and bench-top arbitrary waveform recorders. The internal reference and small MQFP package ease manufacturing tolerances across many SKUs, while CMOS outputs pair directly with mid-range FPGAs. Engineers can implement mixed-channel triggering using the two simultaneous sample clocks.
推荐
Radar and Phased Array Digitizers
The dual 10-bit 60 MSPS architecture simultaneously captures two antenna-element signals in phased-array radar, electronic-warfare receivers, or collision-avoidance sensors. Channel-to-channel timing alignment is critical; integrating both converters on a single silicon die gives the HI5762/6IN superior skew matching (typically sub-sample) compared to discrete designs. The CMOS output interfaces can drive channelized FPGA DSP pipelines for adaptive beamforming.
推荐
推荐产品汇总
工程参考数据： HI5762/6IN ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | HI5762/6IAZ | HI5762/6CN |
|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | MQFP-44 | MQFP-44 - same | MQFP-44 - same |
| Architecture | Dual 10-bit pipelined | Dual 10-bit pipelined | Dual 10-bit pipelined |
| Number of Channels | 2 | 2 | 2 |
| Resolution | 10 bit | 10 bit | 10 bit |
| Sample Rate (per channel) | 60 MSPS | 60 MSPS | 60 MSPS |
| Internal Voltage Reference | Yes | Yes | Yes |
| Digital Output | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Shipping / Packaging Variant | Tray | Tape & Reel (alternate suffix) | Tray - alternate temp grade |
关键差异点
- Drop-in 44-MQFP compatibility with HI5762 family across temperature and shipping suffixes （对比 HI5762/6IAZ)
- Identical silicon die, varying only by industrial/commercial grade （对比 HI5762/6CN)
- Integrated on-chip voltage reference reduces BOM cost by one LDO + reference （对比 External reference design (e.g. ADS8401 family))
设计说明
Estimated: The HI5762/6IN's specified 60 MSPS per-channel SNR is only achieved with a sub-picosecond RMS clock source. Long clock traces, gate-output clock generators, or overshoot/ringing on the CLK_A/CLK_B pins will degrade effective SNR by several dB. Use a low-jitter crystal-oscillator module or a dedicated clock conditioner, keep clock traces matched-length and shielded, and route clocks on a separate layer from analog inputs.
Decouple every AVDD pin locally with a 100 nF X7R ceramic capacitor plus a bulk 10 uF tantalum near the IC; do the same for each DVDD pin. Place the VREF bypass capacitor (typically 10 uF + 100 nF) directly at the VREF pin to filter internal-reference noise. Provide a single, low-impedance analog ground plane under the MQFP-44 with digital ground returns connected only at one point at the power supply to prevent digital switching currents from coupling into the analog inputs.
Estimated: The dual simultaneous channels are sampling at 60 MSPS with 10-bit CMOS outputs switching at the same edge rate. Aggressively terminate the CMOS output bus with series resistors (22-33 ohm) close to the ADC pin to dampen reflections, and avoid running the bus over long distances (>5 cm) on FR-4 to prevent ringing. Place any FPGA capture pins on the same PCB layer as the converter outputs to keep the bus short and length-matched between the two channels.
合规信息
Compliance fields marked unknown because the verified web data did not include explicit RoHS, REACH, lead-free, halogen-free, or conflict-minerals status for HI5762/6IN. The /6IN suffix historically indicates industrial-grade operating temperature; check the latest Renesas product page or distributor listings for current compliance declarations.
