HI5767/4CAZ - 10-Bit 40MSPS ADC, CMOS, 28-SSOP | Renesas
料号： HI5767/4CAZ ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.42 | $8.42 |
| 10 | $7.59 | $75.90 |
| 100 | $6.74 | $674.00 |
| 500 | $5.91 | $2,955.00 |
| 1,000 | $5.18 | $5,180.00 |
HI5767/4CAZ 概述
An analog-to-digital converter (ADC) is a data-acquisition integrated circuit that converts real-world analog signals into discrete digital codes for processing by microcontrollers, DSPs, FPGAs, or ASICs. The HI5767 family sits in the converter hierarchy as follows: ADC -> data converter -> data-acquisition IC -> mixed-signal semiconductor. Pipelined ADCs like the HI5767 use multiple low-resolution stages to achieve high sample rates while keeping per-stage power dissipation modest, making them well suited for intermediate-frequency (IF) sampling, video digitisation, and instrumentation.
Key features of the HI5767/4CAZ include 40 MSPS maximum sampling rate, 10-bit resolution, internal 2.5V bandgap voltage reference, single 5V analog supply, and CMOS/TTL-compatible digital outputs. The pipelined architecture with internal sample-and-hold delivers wide input bandwidth and low power consumption relative to flash converters of equivalent speed, and the SSOP-28 footprint allows compact PCB placement for multi-channel designs.
Typical applications for the HI5767/4CAZ include digital oscilloscopes, IF-sampling communications receivers, CCD/CIS imaging signal chains, medical ultrasound front ends, and industrial inspection cameras. Designers choose this part when a small-footprint 10-bit, 40 MSPS ADC with internal reference and single-supply operation is needed.
Designers should observe standard high-speed mixed-signal layout practice: decouple AVDD with 0.1uF and 10uF ceramics placed within 5 mm of the supply pin, keep analog and digital ground planes separate and join them at a single point near the ADC, and drive the analog input through an AC-coupling network or low-impedance buffer to preserve SFDR. The internal reference eliminates external reference noise pick-up but constrains absolute accuracy to about +/-25 mV initial tolerance.
This page synthesizes distributor pricing, datasheet pinout, drop-in same-package alternatives, and practical layout notes not consolidated in the Renesas datasheet, helping engineers shorten the evaluation cycle.
直接替换替代料： HI5767/4CAZ ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： HI5767/4CAZ （相同外形与封装尺寸） ——差异在于 Package, Resolution, Architecture, Operating Temperature Range, Data Interface.
快速对比工具——选择替代料号进行并排对比：
HI5766KCAZ
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$5.6 / 个
查看数据手册 →HI5714/7CB-T
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$9.2 / 个
查看数据手册 →ADS901E/1KG4
✅ 直接替换✓ 有现货
$4.12 / 个
查看数据手册 →ADS8401IPFBRG4
✅ 直接替换✓ 有现货
$11.75 / 个
查看数据手册 →ADS7824UB/1KG4
✅ 直接替换✓ 有现货
$9.4 / 个
查看数据手册 →HI5767/4CAZ 最大额定值与电气特性
| 分辨率 | 10 bit |
| Number of Channels | 1 |
| Sample Rate | 40 MSPS |
| Architecture | Pipelined |
| Input Type | Differential / Single-ended |
| Analog Supply Voltage | 5 V (single supply) |
| Digital Supply Voltage | 3 V to 5 V |
| Internal Voltage Reference | Yes (bandgap, 2.5 V nominal) |
| Sample-and-Hold | Internal |
| Data Interface | Parallel CMOS/TTL |
| 工作温度范围 | 0 C to +70 C (commercial) |
| Package / Pin Count | 28-SSOP/QSOP |
| 安装类型 | Surface Mount |
| Process Technology | CMOS |
| RoHS 状态 | Compliant |
HI5767/4CAZ 引脚配置
| 引脚 1 | AIN — Analog input (positive) |
| 引脚 2 | AINB — Complementary analog input |
| 引脚 3 | CM — Common-mode voltage bypass |
| 引脚 4 | AGND — Analog ground |
| 引脚 5 | AVDD — Analog +5 V supply |
| 引脚 6 | REFCOMP — Reference compensation capacitor |
| 引脚 7 | REFOUT — Internal 2.5 V bandgap reference output |
| 引脚 8 | REFGND — Reference ground |
| 引脚 9 | DRVDD — Digital output driver supply |
| 引脚 10 | DRGND — Digital output driver ground |
| 引脚 11 | CLK — Sample clock input |
| 引脚 12 | CLKB — Complementary clock input |
| 引脚 13 | D9 (MSB) — Data output bit 9 (MSB) |
| 引脚 14 | D8 — Data output bit 8 |
| 引脚 15 | D7 — Data output bit 7 |
| 引脚 16 | D6 — Data output bit 6 |
| 引脚 17 | D5 — Data output bit 5 |
| 引脚 18 | D4 — Data output bit 4 |
| 引脚 19 | D3 — Data output bit 3 |
| 引脚 20 | D2 — Data output bit 2 |
| 引脚 21 | D1 — Data output bit 1 |
| 引脚 22 | D0 (LSB) — Data output bit 0 (LSB) |
| 引脚 23 | DRVDD — Digital output driver supply (second pin) |
| 引脚 24 | DRGND — Digital output driver ground (second pin) |
| 引脚 25 | AVDD — Analog +5 V supply (second pin) |
| 引脚 26 | AGND — Analog ground (second pin) |
| 引脚 27 | AVDD — Analog +5 V supply (third pin) |
| 引脚 28 | NC — Not connected (per datasheet) |
典型应用
HI5767/4CAZ 适用于 6 应用s: Digital Oscilloscope Front-End, IF Sampling Communications Receiver, CCD/CIS Imaging Signal Chain, Medical Ultrasound Beamformer, Industrial Inspection Camera, Portable Test & Measurement Equipment.
Digital Oscilloscope Front-End
The HI5767/4CAZ fits digital oscilloscope front-end digitisation because its 40 MSPS sample rate exceeds the Nyquist requirement for 10-15 MHz input bandwidths typical of mid-range scopes, and the 10-bit resolution yields ~60 dB dynamic range. Designers place the ADC after the attenuator/buffer chain and drive AIN with a low-impedance op-amp to maximise SFDR. The internal bandgap reference eliminates an external reference IC, simplifying the BOM and shrinking PCB area in 4-channel scope cards.
推荐
IF Sampling Communications Receiver
The HI5767/4CAZ suits IF-sampling software-defined radio (SDR) receivers where the 10.7 MHz or 21.4 MHz IF must be digitised directly. The 40 MSPS sample rate places the IF comfortably in the second Nyquist zone when clocked from a 30 MHz reference, and the pipelined core delivers the SFDR needed for demodulation. The on-chip sample-and-hold relaxes the analog-input driver design, while the internal 2.5V reference centres the input common-mode for AC-coupled IF transformers.
推荐
CCD/CIS Imaging Signal Chain
Imaging systems built around CCD or CIS sensors use the HI5767/4CAZ to digitise pixel-stream outputs at 20-40 MSPS. The internal sample-and-hold accepts the sensor's reset and signal feed levels directly, and the 10-bit resolution matches typical 8-bit display depth plus processing headroom for gamma correction. The 28-SSOP package's compact footprint supports multi-channel line-scan cameras where four ADCs fit on a 30 mm x 30 mm analog PCB.
推荐
Medical Ultrasound Beamformer
Mid-frequency ultrasound front ends digitise the bandlimited RF signal at 20-40 MSPS and feed the digital beamformer. The HI5767/4CAZ's 10-bit pipelined core achieves ~55 dB SINAD at clinical frequencies, sufficient for B-mode imaging up to 128 channels. Designers buffer each transducer channel with a high-speed op-amp before the ADC and pair the digital outputs with an FPGA to perform delay-and-sum beamforming. The commercial temperature grade suits cart-based ultrasound systems.
推荐
Industrial Inspection Camera
Machine-vision and industrial inspection cameras stream digitised pixel data to an FPGA or image processor at rates up to 40 MSPS. The HI5767/4CAZ handles line-scan and area-scan sensors at video frame rates and provides clean 10-bit grayscale depth for defect detection algorithms. The CMOS digital outputs interface directly to 3.3V FPGAs with no level shifting, and the internal reference reduces the BOM count for cost-sensitive factory-floor designs.
推荐
Portable Test & Measurement Equipment
Handheld oscilloscopes, spectrum analysers, and bench DMMs use the HI5767/4CAZ to keep BOM cost and power budget low while delivering 40 MSPS capture rate. The 5V single-supply operation pairs with Li-ion powered boost regulators, and the CMOS digital outputs minimise logic power. The 28-SSOP package fits behind the analog input BNC, and the internal reference trims the calibration burden in factory testing.
推荐
推荐产品汇总
工程参考数据： HI5767/4CAZ ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | HI5766KCAZ | HI5714/7CB-T | ADS901E/1KG4 | ADS8401IPFBRG4 | ADS7824UB/1KG4 |
|---|---|---|---|---|---|---|
| Package | 28-SSOP/QSOP | 28-SSOP/QSOP - same | 28-SSOP/QSOP - same | 28-SSOP - same | 28-SSOP (alt body) | 28-SSOP - same |
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 10 bit | 8 bit | 8 bit | 10 bit | 16 bit | 12 bit |
| Sample Rate | 40 MSPS | 40 MSPS | 40 MSPS | 40 MSPS | 1.25 MSPS | 0.2 MSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | SAR | SAR |
| Analog Supply | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C | 0 C to +70 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
关键差异点
- Internal bandgap reference eliminates external reference IC （对比 ADS8401IPFBRG4)
- Pipelined architecture at 40 MSPS outperforms SAR alternatives in bandwidth （对比 ADS7824UB/1KG4)
- Same-family pinout across 8-bit and 10-bit speed grades （对比 HI5766KCAZ)
设计说明
Decouple AVDD with a 0.1 uF X7R ceramic placed within 5 mm of the analog supply pin and add a 10 uF bulk tantalum or ceramic in parallel. Pin 23/24 (DRVDD/DRGND) drive the parallel CMOS bus and should be similarly decoupled. Sequencing is not required; both rails can ramp together.
Use a single ground plane with analog and digital portions split under the ADC and joined at a single point near the AGND/DRGND pins. Route the parallel digital output bus away from the analog input traces, and keep the CLK trace short and matched in length to avoid sample-time skew. The reference bypass capacitor on REFCOMP must be a low-leakage 0.1 uF ceramic within 3 mm of the pin.
Drive AIN/AINB through a low-impedance AC-coupled buffer such as a transformer or high-speed op-amp; the on-chip sample-and-hold presents a switched-capacitor load that can degrade SFDR if driven by more than ~50 ohm source impedance. Keep the analog input trace length under 10 mm and use a 50 ohm microstrip on the analog layer.
合规信息
RoHS compliant per Renesas product declaration; commercial temperature grade (0 C to +70 C). AEC-Q100 not applicable for the /CAZ commercial grade - request /IAZ or industrial-grade suffix for automotive-grade qualification if needed.
