HI5767/6CA - 10-Bit 60MSPS ADC w/ Reference | SSOP-28 | Renesas
料号： HI5767/6CA ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $5.08 | $5.08 |
| 10 | $4.65 | $46.50 |
| 100 | $4.1 | $410.00 |
| 500 | $3.72 | $1,860.00 |
| 1,000 | $3.4 | $3,400.00 |
HI5767/6CA 概述
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes, enabling real-world signals (voltage, current, temperature, RF) to be processed by digital systems such as FPGAs, DSPs, and microcontrollers. Within the data-converter hierarchy, the HI5767/6CA belongs to the successive-approximation/pipelined SAR-ADC family, which occupies the middle ground between slow, high-resolution SAR converters and very high-speed flash converters. It is widely used in cost-sensitive mid-bandwidth systems where 8-10 bit resolution is sufficient.
Key features of the HI5767/6CA include a 60 MHz maximum sampling rate, 10-bit resolution, internal 2.5 V voltage reference, single +5 V analog supply operation, and low power CMOS design. The pipelined architecture multiplies conversion throughput while keeping per-sample latency short, and the parallel digital interface simplifies downstream FPGA or ASIC capture. Internal reference and integrated sample-and-hold reduce the external BOM to a small number of bypass capacitors and a single decoupling network.
Typical applications include video digitisation, IF sampling in communications receivers, CCD imaging front-ends, instrumentation and digital oscilloscope front-ends, and high-speed data acquisition cards. The combination of internal reference, low pin count, and 60 MSPS throughput makes the part attractive for legacy designs in industrial imaging and communications infrastructure where a 10-bit conversion is adequate.
Designers should observe single-supply +5 V operation, provide adequate power-supply decoupling, and ensure the analog input drive network maintains the rated input bandwidth at the full-scale input of the converter. The wide SSOP-28 footprint simplifies PCB routing on multi-layer boards.
This page synthesises distributor pricing, drop-in alternatives, and design considerations not found in the manufacturer datasheet alone, helping engineers select, qualify, and source the HI5767/6CA efficiently.
直接替换替代料： HI5767/6CA ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： HI5767/6CA （相同外形与封装尺寸） ——差异在于 Package, Architecture, Sampling Rate, Input Type, Resolution.
快速对比工具——选择替代料号进行并排对比：
HI5767/6CA-T
✅ 直接替换📋 参考替代料（不在目录中）
HI5767/4CB-T
✅ 直接替换✓ 有现货
$4.95 / 个
查看数据手册 →HI5767/4CBZ-T
✅ 直接替换✓ 有现货
$8.25 / 个
查看数据手册 →HI5766KCAZ
✅ 直接替换✓ 有现货
$5.6 / 个
查看数据手册 →HI5714/7CB-T
✅ 直接替换✓ 有现货
$9.2 / 个
查看数据手册 →ADS901E/1K
✅ 直接替换✓ 有现货
$2.59 / 个
查看数据手册 →HI5767/6CA 最大额定值与电气特性
| 分辨率 | 10 bit |
| 采样率 | 60 MSPS (max) |
| Architecture | Pipelined CMOS ADC |
| Number of Channels | 1 |
| Input Type | Single-ended analog |
| 电源电压 | 5 V (single supply) |
| Internal Reference | Yes (2.5 V typical) |
| Digital Interface | Parallel CMOS |
| 封装 | SSOP-28 |
| 安装类型 | Surface Mount |
| Process Technology | CMOS |
| RoHS 状态 | Compliant (per Renesas product page) |
HI5767/6CA 引脚配置
| 引脚 1 | AVDD — Analog +5 V supply |
| 引脚 2 | AVSS — Analog ground |
| 引脚 3 | AIN — Analog input |
| 引脚 4 | REFT — Top reference decoupling |
| 引脚 5 | REFB — Bottom reference decoupling |
| 引脚 6 | REFOUT — Internal 2.5 V reference output |
| 引脚 7 | REFIN — Reference input (bypass to REFOUT or external ref) |
| 引脚 8 | CLKBYP — Clock buffer bypass/decoupling |
| 引脚 9 | CLK — Clock input |
| 引脚 10 | CLKGND — Clock ground |
| 引脚 11 | DVDD — Digital +5 V supply |
| 引脚 12 | DVSS — Digital ground |
| 引脚 13 | OE — Output enable (active high) |
| 引脚 14 | D9 (MSB) — Data output bit 9 |
| 引脚 15 | D8 — Data output bit 8 |
| 引脚 16 | D7 — Data output bit 7 |
| 引脚 17 | D6 — Data output bit 6 |
| 引脚 18 | D5 — Data output bit 5 |
| 引脚 19 | D4 — Data output bit 4 |
| 引脚 20 | D3 — Data output bit 3 |
| 引脚 21 | D2 — Data output bit 2 |
| 引脚 22 | D1 — Data output bit 1 |
| 引脚 23 | D0 (LSB) — Data output bit 0 |
| 引脚 24 | DRDY — Data ready / convert signal |
| 引脚 25 | PD — Power-down (active high) |
| 引脚 26 | NC — Not connected |
| 引脚 27 | NC — Not connected |
| 引脚 28 | AVDD — Analog +5 V supply |
典型应用
HI5767/6CA 适用于 6 应用s: Video Digitisation Front-End, IF Sampling for Communications Receivers, CCD Imaging Front-End, Digital Oscilloscope Front-End, High-Speed Data Acquisition Card, Set-Top Box and Cable Modem Tuner.
Video Digitisation Front-End
The HI5767/6CA's 60 MSPS sampling rate and 10-bit resolution make it well suited to digitising standard-definition and intermediate-frequency video signals in broadcast, surveillance, and industrial imaging systems. Placed at the front of an FPGA-based video pipeline with a single +5 V supply and internal 2.5 V reference, it eliminates the need for an external reference IC, simplifying the analogue front-end. Its pipelined CMOS architecture holds conversion latency low (typically 3-4 clock cycles), which simplifies downstream timing closure for line-locked video capture. Compared with a flash ADC, the HI5767/6CA offers far lower power dissipation at this resolution, allowing multi-channel capture boards to stay within thermal budgets without active cooling.
推荐
IF Sampling for Communications Receivers
In digital-IF receiver designs, the HI5767/6CA digitises intermediate-frequency signals after the mixer stage, enabling digital demodulation in the baseband processor. Its 60 MSPS throughput comfortably covers IF bandwidths up to approximately 25 MHz (Nyquist), making it appropriate for narrowband radio, satellite IF, and legacy cellular infrastructure. The internal 2.5 V reference and single +5 V supply simplify the RF board stack-up, while the parallel CMOS output drives an FPGA demodulator directly without an extra buffer. Designers benefit from the part's established second-source availability via Renesas/Rochester Electronics, which keeps long-lifecycle communications products in production.
推荐
CCD Imaging Front-End
The HI5767/6CA is well-matched to CCD line-scan and area-scan imagers used in industrial inspection, document scanning, and machine vision, where 10-bit pixel depth and 60 MSPS conversion support multi-megapixel per-second throughput. Its CMOS process provides low noise floor at pixel rates typical of CCD output amplifiers, and the integrated sample-and-hold removes the need for an external track-and-hold stage. Paired with a low-jitter clock source, the converter delivers clean digitisation that preserves the CCD's dynamic range, critical for high-contrast scenes in production-line inspection. The SSOP-28 footprint integrates easily into multi-channel camera boards.
推荐
Digital Oscilloscope Front-End
Cost-sensitive 100-200 MHz digital oscilloscopes and handheld scopes often rely on a 10-bit, 60 MSPS front-end ADC to provide sufficient timebase resolution and amplitude accuracy. The HI5767/6CA's pipelined architecture and parallel output interface pair naturally with an FPGA-based capture memory and trigger engine. Its 5 V single-supply operation reduces power-supply complexity inside a compact handheld enclosure, while the internal reference keeps bill-of-materials cost low. When paired with an attenuator/amplifier front-end and AC/DC coupling network, the converter enables sub-mV sensitivity through oversampling and averaging.
推荐
High-Speed Data Acquisition Card
PCI/PCIe-based data acquisition cards for industrial test, ultrasound, and vibration analysis commonly use the HI5767/6CA as the ADC front-end. Its 60 MSPS rate and 10-bit resolution cover ultrasonic transducer arrays operating in the 5-15 MHz range with comfortable margin, and the parallel CMOS output feeds an FPGA that performs beamforming or FFT before sending results over the bus. The internal reference and low pin count keep the analogue front-end compact, leaving board area for multi-channel signal conditioning. Long-term availability through Rochester Electronics makes the part attractive for medical and industrial systems with multi-year product lifecycles.
推荐
Set-Top Box and Cable Modem Tuner
Digital cable set-top boxes and early cable-modem designs use the HI5767/6CA in the downstream QAM/ATSC demodulator chain, where a 60 MSPS, 10-bit converter offers the resolution needed for symbol-level decoding while keeping tuner cost low. The internal 2.5 V reference and CMOS process allow the converter to coexist on the same +5 V rail as the tuner IC, simplifying the power tree. The pipelined latency is acceptable for the buffered demodulation stages used in consumer video. Its SSOP-28 package and standard pinout ease assembly on high-volume consumer electronics lines.
推荐
推荐产品汇总
工程参考数据： HI5767/6CA ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | HI5767/6CA-T | HI5767/4CB-T | HI5767/4CBZ-T | HI5766KCAZ | ADS901E |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Package | SSOP-28 | SSOP-28 - same | SSOP-28 - same | SSOP-28 - same | SSOP-28 - same | SSOP-28 - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 8 bit | 10 bit |
| Sampling Rate | 60 MSPS | 60 MSPS | 20 MSPS | 20 MSPS | 60 MSPS | 20 MSPS |
| Supply Voltage | +5 V single | +5 V | +5 V | +5 V | +5 V | +5 V |
| Digital Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Architecture | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS |
关键差异点
- Highest sample-rate option within the HI5767 SSOP-28 family （对比 HI5767/4CB-T)
- 10-bit resolution with parallel CMOS output （对比 HI5766KCAZ)
- Internal 2.5 V reference reduces external BOM （对比 ADS901E)
设计说明
The HI5767/6CA operates from a single +5 V supply split into separate analog (AVDD) and digital (DVDD) rails. Place a 10 uF bulk capacitor and a 100 nF ceramic decoupling capacitor within 5 mm of each AVDD/DVDD pin pair. Star-ground analog and digital returns at the converter's exposed pad to prevent digital switching currents from corrupting the analog input path. Aggressive power-supply rejection at the analog rail directly improves spurious-free dynamic range, so use an LDO rather than a switching regulator for AVDD when the design is noise-sensitive.
Treat the analog input trace as a 50 ohm transmission line if the input frequency content exceeds 10 MHz, and keep the trace length below 25 mm to avoid reflections. Surround the analog input with a continuous ground guard on the same PCB layer, with vias stitching the guard to the underlying ground plane every 5 mm. Place the REFOUT bypass capacitor (typically 100 nF) directly at the REFOUT pin and route REFIN as a short, low-impedance trace. The clock input is the most critical signal after AIN - place the clock source within 20 mm and use a series damping resistor if overshoot is observed.
Do not exceed the absolute maximum analog input voltage of AVDD + 0.3 V; transient over-voltage can latch up the CMOS input. Always enable the output enable (OE) line only after the clock is stable and the reference has settled (typically 100 us after power-up) to avoid spurious digital output codes. If the application demands better than 10-bit ENOB, oversample and average multiple conversions in the FPGA - the HI5767/6CA's pipelined noise floor permits an effective +1 bit gain under 4x oversampling. Finally, ensure the CLK duty cycle stays within 45-55% because jitter above 5 ps RMS will degrade SNR noticeably at 60 MSPS.
合规信息
RoHS and lead-free status per Renesas product page; AEC-Q100 not applicable - this is a commercial/industrial-grade ADC. REACH and conflict-minerals declarations not exposed in the provided data.
