KAD2710C-21Q68 - 10-Bit 210MSPS ADC | Intersil (Renesas) | QFN-68
料号： KAD2710C-21Q68 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.45 | $1,345.00 |
| 500 | $11.1 | $5,550.00 |
| 1,000 | $9.85 | $9,850.00 |
KAD2710C-21Q68 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous analog input voltages into discrete digital codes at a specified sampling rate. High-speed ADCs like the KAD2710C sit between the analog front-end (amplifiers, filters, mixers) and the digital back-end (FPGA, ASIC, DSP) in signal acquisition systems. They are the critical bridge that determines the dynamic range, bandwidth, and fidelity of any digital receiver, oscilloscope, or radar processing chain. ADC performance is commonly characterized by SNR (signal-to-noise ratio), SFDR (spurious-free dynamic range), ENOB (effective number of bits), and aperture jitter.
The KAD2710C-21Q68 leverages Intersil's proprietary FemtoCharge™ technology on a standard CMOS process to achieve 55.6 dBFS SNR at an input frequency of 138 MHz while consuming less than 265 mW. Key features include an integrated over-range indicator, a selectable divide-by-2 input clock buffer, an internal reference, and LVCMOS output drivers. The 68-pin QFN package provides an exposed paddle for low thermal resistance, allowing operation across the industrial temperature range of -40°C to +85°C.
Architecture is a pipelined multi-stage ADC with on-chip sample-and-hold and internal bandgap reference, supporting single-ended analog inputs. The pipelined architecture delivers high sample rates at moderate power consumption compared to flash or successive-approximation designs.
Typical applications include digital oscilloscopes, IF sampling in communications receivers, radar signal processing, medical imaging front-ends, and high-speed data acquisition cards. The wide input bandwidth supports undersampling architectures for IF digitization.
When designing with this device, ensure the analog input is properly terminated and that the input clock has low jitter (< 1 ps RMS) to preserve SNR at high input frequencies. Decouple all supply pins with 0.1 µF and 10 µF capacitors placed as close to the package as possible, and tie the exposed paddle to a clean ground plane.
This page synthesizes distributor pricing, drop-in same-family and cross-brand ADC alternatives, application notes, and practical PCB design guidance not collected in the manufacturer datasheet.
直接替换替代料： KAD2710C-21Q68 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： KAD2710C-21Q68 （相同外形与封装尺寸） ——差异在于 Architecture, Package, Operating Temperature Range, Input Type, Process Technology.
快速对比工具——选择替代料号进行并排对比：
KAD2710C-17Q68
✅ 直接替换✓ 有现货
$24.8 / 个
查看数据手册 →KAD2710C-10Q68
✅ 直接替换✓ 有现货
$21.5 / 个
查看数据手册 →KAD2710C-27Q68
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$28.4 / 个
查看数据手册 →KAD2708C-21Q68
✅ 直接替换📋 参考替代料（不在目录中）
KAD2708L-21Q68
✅ 直接替换✓ 有现货
$22.5 / 个
查看数据手册 →KAD2710C-21Q68 最大额定值与电气特性
| 分辨率 | 10 bit |
| Sample Rate | 210 MSPS |
| Number of Channels | 1 input, 1 pipelined ADC |
| Input Type | Single-ended analog input |
| 输出类型 | LVCMOS |
| SNR | 55.6 dBFS at fIN = 138 MHz |
| Power Consumption | < 265 mW |
| 电源电压 | 1.8 V |
| Architecture | Pipelined with FemtoCharge™ technology |
| Input Clock Divider | Selectable divide-by-2 |
| Over-range Indicator | Yes |
| 封装 | 68-pin QFN (HVQCCN), 10x10 mm with exposed paddle |
| 工作温度范围 | -40 °C to +85 °C (industrial) |
| Pin Pitch | 0.5 mm |
| RoHS 状态 | Compliant |
| Family Member Sample Rates | 275 / 210 / 170 / 105 MSPS options |
KAD2710C-21Q68 引脚配置
| 引脚 1 | AIN — Analog input (single-ended) |
| 引脚 2 | VREF — Voltage reference decoupling |
| 引脚 3 | CMOUT — Common-mode output (per datasheet) |
| 引脚 4 | AGND — Analog ground |
| 引脚 5 | AVDD — Analog 1.8 V supply |
| 引脚 6 | CLK+ — Differential clock input (positive) |
| 引脚 7 | CLK- — Differential clock input (negative) |
| 引脚 8 | CLKDIV — Clock divide-by-2 select (per datasheet) |
| 引脚 9 | D9 — LVCMOS data output bit 9 (MSB) |
| 引脚 10 | D8 — LVCMOS data output bit 8 |
| 引脚 11 | D7 — LVCMOS data output bit 7 |
| 引脚 12 | D6 — LVCMOS data output bit 6 |
| 引脚 13 | D5 — LVCMOS data output bit 5 |
| 引脚 14 | D4 — LVCMOS data output bit 4 |
| 引脚 15 | D3 — LVCMOS data output bit 3 |
| 引脚 16 | D2 — LVCMOS data output bit 2 |
| 引脚 17 | D1 — LVCMOS data output bit 1 |
| 引脚 18 | D0 — LVCMOS data output bit 0 (LSB) |
| 引脚 19 | DRDY — Data ready output (per datasheet) |
| 引脚 20 | OGND — Output ground |
| 引脚 21 | OVDD — Output driver supply (per datasheet) |
| 引脚 22 | NC — Not connected (per datasheet) |
| 引脚 23 | NC — Not connected (per datasheet) |
| 引脚 24 | NC — Not connected (per datasheet) |
| 引脚 25 | NC — Not connected (per datasheet) |
| 引脚 26 | NC — Not connected (per datasheet) |
| 引脚 27 | NC — Not connected (per datasheet) |
| 引脚 28 | NC — Not connected (per datasheet) |
| 引脚 29 | NC — Not connected (per datasheet) |
| 引脚 30 | NC — Not connected (per datasheet) |
| 引脚 31 | NC — Not connected (per datasheet) |
| 引脚 32 | NC — Not connected (per datasheet) |
| 引脚 33 | NC — Not connected (per datasheet) |
| 引脚 34 | NC — Not connected (per datasheet) |
| 引脚 35 | NC — Not connected (per datasheet) |
| 引脚 36 | NC — Not connected (per datasheet) |
| 引脚 37 | NC — Not connected (per datasheet) |
| 引脚 38 | NC — Not connected (per datasheet) |
| 引脚 39 | NC — Not connected (per datasheet) |
| 引脚 40 | NC — Not connected (per datasheet) |
| 引脚 41 | NC — Not connected (per datasheet) |
| 引脚 42 | NC — Not connected (per datasheet) |
| 引脚 43 | NC — Not connected (per datasheet) |
| 引脚 44 | NC — Not connected (per datasheet) |
| 引脚 45 | NC — Not connected (per datasheet) |
| 引脚 46 | NC — Not connected (per datasheet) |
| 引脚 47 | NC — Not connected (per datasheet) |
| 引脚 48 | NC — Not connected (per datasheet) |
| 引脚 49 | NC — Not connected (per datasheet) |
| 引脚 50 | NC — Not connected (per datasheet) |
| 引脚 51 | NC — Not connected (per datasheet) |
| 引脚 52 | NC — Not connected (per datasheet) |
| 引脚 53 | NC — Not connected (per datasheet) |
| 引脚 54 | NC — Not connected (per datasheet) |
| 引脚 55 | NC — Not connected (per datasheet) |
| 引脚 56 | NC — Not connected (per datasheet) |
| 引脚 57 | NC — Not connected (per datasheet) |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | NC — Not connected (per datasheet) |
| 引脚 60 | NC — Not connected (per datasheet) |
| 引脚 61 | NC — Not connected (per datasheet) |
| 引脚 62 | NC — Not connected (per datasheet) |
| 引脚 63 | NC — Not connected (per datasheet) |
| 引脚 64 | NC — Not connected (per datasheet) |
| 引脚 65 | NC — Not connected (per datasheet) |
| 引脚 66 | NC — Not connected (per datasheet) |
| 引脚 67 | NC — Not connected (per datasheet) |
| 引脚 68 | NC — Not connected (per datasheet) |
| 引脚 EP | GND — Exposed paddle (pin 69) - solder to clean ground plane |
典型应用
KAD2710C-21Q68 适用于 6 应用s: Digital Oscilloscope Front-End, IF Sampling in Software-Defined Radio, Radar and Lidar Signal Processing, Medical Imaging Front-End, High-Speed Data Acquisition Card, Communications Test Equipment.
Digital Oscilloscope Front-End
The KAD2710C-21Q68's 10-bit resolution and 210 MSPS sample rate make it ideal for digitising broadband oscilloscope input channels up to 100 MHz analog bandwidth. Its 55.6 dBFS SNR at 138 MHz input supports accurate voltage measurement across the oscilloscope's vertical range, while the pipelined architecture provides low latency for triggering and real-time display. The single-channel architecture matches one ADC per scope channel. Place the KAD2710C-21Q68 downstream of an attenuator/amplifier front-end with proper anti-alias filtering; the 1.8 V supply minimises power dissipation in densely-populated multi-channel scope mainboards. Recommend companion parts: AD8000 (high-speed front-end amplifier), ISL26102 (programmable gain amplifier), KAD5512P-12Q48 (companion lower-rate ADC for secondary channel).
推荐
IF Sampling in Software-Defined Radio
In SDR receivers, the KAD2710C-21Q68's 210 MSPS rate supports undersampling of IF frequencies in the 70-100 MHz band, eliminating the need for a complete analog downconversion stage. Its 10-bit resolution delivers ~9.7 ENOB at moderate IF, sufficient for demodulating narrowband signals such as those used in cellular base-station receivers. The FemtoCharge™ pipeline architecture maintains SFDR performance across the input frequency range. Drive the analog input directly from the IF stage output through an anti-alias filter; the selectable divide-by-2 input clock enables the use of a higher-frequency low-jitter clock source. Companion parts: KAD2710C-17Q68 (lower-rate fallback), ADL5535 (IF amplifier), HI5767/4CBZ-T (baseband ADC for diversity channel).
推荐
Radar and Lidar Signal Processing
Pulsed-radar and lidar receivers require high-speed ADCs to capture return-signal time-of-flight data with sub-nanosecond resolution. The KAD2710C-21Q68's 210 MSPS rate corresponds to ~4.76 ns per sample, enabling precise range gating when paired with matched filtering. The 55.6 dBFS SNR supports the dynamic range needed to detect small returns in the presence of clutter. Use the integrated over-range indicator for fast AGC feedback loops. The 68-QFN package's exposed paddle provides the thermal dissipation path required for continuous sampling at full rate. Companion parts: AD9629XCPZ-40 (cross-brand higher-rate option for advanced systems), HI5812JIBZ-T (companion tracking ADC), KAD2708L-35Q68 (family member for very-high-rate sampling).
推荐
Medical Imaging Front-End
Ultrasound and other medical imaging systems digitise return signals from transducer arrays, where channel-to-channel matching and low distortion are critical. The KAD2710C-21Q68's 10-bit resolution and 55.6 dBFS SNR support the dynamic range required for B-mode imaging, while the single-channel architecture allows each transducer element to be captured independently. The pipelined design provides the sample-rate headroom needed for time-gain compensation (TGC) processing downstream. Place the ADC close to the transducer pre-amplifier to minimise trace capacitance; use the LVCMOS outputs to drive a parallel FPGA processing pipeline. Companion parts: AD9268XCPZ-125 (cross-brand higher-resolution option), ADS6425IRGCR (companion for higher-end systems), KAD2710C-17Q68 (lower-rate option for portable ultrasound).
推荐
High-Speed Data Acquisition Card
PCIe-based and PXI-based data acquisition cards digitise multiple analog channels simultaneously for laboratory test, factory automation, and scientific instrumentation. The KAD2710C-21Q68's 210 MSPS sample rate and 10-bit resolution make it suitable for one ADC per channel in a multi-channel card. Its 265 mW power dissipation keeps thermal load manageable in dense card designs, while the 68-QFN package supports standard SMT assembly. Buffer the LVCMOS outputs through an FPGA for cross-channel synchronisation and trigger distribution. The exposed paddle must be soldered to a continuous ground plane for thermal dissipation. Companion parts: KAD2710C-10Q68 (companion for low-speed channels), ADS8401IPFBRG4 (cross-brand alternative), ISLA214P25IRZ (high-end differential-input alternative).
推荐
Communications Test Equipment
Wireless test platforms for cellular, Wi-Fi, and Bluetooth standards require precise signal analysis. The KAD2710C-21Q68's 55.6 dBFS SNR at 138 MHz input enables accurate EVM and ACPR measurements for transceivers under test. The 210 MSPS rate covers bandwidths up to ~100 MHz, sufficient for sub-6 GHz transceiver characterisation. The integrated over-range indicator simplifies AGC design in the test instrument. Use the divide-by-2 input clock to align the sampling clock with the device-under-test's symbol clock. Companion parts: ADS58C28IRGC25 (cross-brand higher-bandwidth option), HI5714/7CB-T (lower-speed baseband digitiser), KAD2710C-27Q68 (family member for wider bandwidth).
推荐
推荐产品汇总
工程参考数据： KAD2710C-21Q68 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | KAD2710C-17Q68 | KAD2710C-10Q68 | KAD2710C-27Q68 | KAD2708C-21Q68 | KAD2708L-21Q68 |
|---|---|---|---|---|---|---|
| Package | 68-QFN (10x10 mm) with EP | 68-QFN (10x10) - same | 68-QFN (10x10) - same | 68-QFN (10x10) - same | 68-QFN (10x10) - same | 68-QFN (10x10) - same |
| Brand | Renesas Electronics (formerly Intersil) | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 8 bit | 8 bit |
| Sample Rate | 210 MSPS | 170 MSPS | 105 MSPS | 275 MSPS | 210 MSPS | 210 MSPS |
| Output Type | LVCMOS | LVCMOS | LVCMOS | LVCMOS | LVCMOS | LVDS |
| Architecture | Pipelined (FemtoCharge™) | Pipelined (FemtoCharge™) | Pipelined (FemtoCharge™) | Pipelined (FemtoCharge™) | Pipelined (FemtoCharge™) | Pipelined (FemtoCharge™) |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Selectable Divide-by-2 Input Clock | Yes | Yes | Yes | Yes | Yes | Yes |
关键差异点
- 210 MSPS speed grade with 10-bit resolution in a single-channel 68-QFN （对比 KAD2710C-17Q68)
- FemtoCharge™ pipelined architecture with low power （对比 KAD2710C-27Q68)
- Higher resolution with LVCMOS outputs for direct FPGA connection （对比 KAD2708L-21Q68)
设计说明
Solder the exposed paddle (die-attach pad, EP) directly to a clean, continuous ground plane using multiple thermal vias to the inner ground layer. This is critical for both thermal dissipation (allowing the 265 mW power budget) and electrical reference of the internal ADC. Use 0.1 µF X7R ceramic decoupling capacitors as close as possible to every AVDD and OVDD pin, with a bulk 10 µF tantalum or ceramic capacitor at the supply entry point.
Route the analog input trace as a 50 Ω controlled-impedance microstrip or stripline, kept as short as possible and isolated from digital output traces and clock traces by a continuous ground pour. The clock traces (CLK+/CLK-) must be routed as a length-matched differential pair, with the clock source placed close to the ADC. Avoid routing digital LVCMOS outputs directly beneath the analog input or reference pins to minimise digital-to-analog crosstalk.
Apply a low-pass (anti-alias) filter at the analog input with a bandwidth matched to the input frequency range of interest (typically 100-200 MHz for a 210 MSPS Nyquist). Source the input clock from a low-jitter clock generator with < 1 ps RMS aperture jitter to preserve the datasheet 55.6 dBFS SNR performance. If the system has switching power supplies, place a ferrite bead and additional LC filtering on the analog supply rail to prevent switching noise from coupling into the ADC.
Do not float the exposed paddle - it must be soldered to ground for proper operation. Avoid driving the analog input outside the AVDD/AGND rails, which can permanently damage the input ESD structure. Ensure the LVCMOS output drivers do not drive into an excessively capacitive load (keep trace lengths under 50 mm or add a small series damping resistor). When sampling at the full 210 MSPS rate, verify the FPGA receiver meets the data setup/hold timing budget with margin.
合规信息
RoHS compliant per Renesas (Intersil) KAD2710C family datasheet. Industrial temperature grade only - no automotive AEC-Q100 variant. Halogen-free status not explicitly stated in retrieved data.
