KSZ9897RTXC - 7-Port Gigabit Managed Ethernet Switch | Microchip
料号： KSZ9897RTXC ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.1 | $131.00 |
| 100 | $11.62 | $1,162.00 |
| 500 | $10.2 | $5,100.00 |
| 1,000 | $9.05 | $9,050.00 |
KSZ9897RTXC 概述
A managed Layer-2 Gigabit Ethernet switch is a network bridge device that forwards Ethernet frames between multiple physical ports based on a MAC address table, while exposing a management plane (registers, MIB counters, ACLs, VLANs) for configuration and diagnostics. Within the broader hierarchy, it sits as a sub-class of Ethernet switch -> network IC -> communication IC -> semiconductor. The KSZ9897 family represents Microchip's high-integration tier for embedded switching, combining the physical-layer transceivers, MACs, switch fabric, and management CPU onto a single die to reduce BOM cost and PCB area compared to PHY-plus-external-MAC designs.
Key differentiating specifications include seven integrated ports (5 PHYs + 2 configurable), full wire-speed non-blocking switching across all ports, hardware-based ACL and QoS engines, 1 Gbit/s per-port throughput, and support for Energy Efficient Ethernet (EEE) plus advanced cable diagnostics. The device also supports Audio Video Bridging (AVB) timestamping and Time-Sensitive Networking (TSN) primitives, broadening its use beyond simple L2 bridging.
Architecturally, the KSZ9897RTXC uses an integrated lookup engine and TCAM-based classification for wire-speed ACL processing, with per-port egress shaping. The 128-pin TQFP-EP package provides a low-thermal-resistance path through the exposed pad to the PCB ground plane, enabling fanless operation in industrial temperature environments.
Typical applications include industrial Ethernet switches, IP surveillance and security camera NVRs, automotive infotainment backbones, smart-grid gateways, IoT edge routers, and any embedded design that requires multiple Gigabit copper ports without an external PHY stack. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： KSZ9897RTXC ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： KSZ9897RTXC （相同外形与封装尺寸） ——差异在于 Package, Number of Ports, Product Type, RoHS Status.
快速对比工具——选择替代料号进行并排对比：
KSZ9897RTXI
✅ 直接替换📋 参考替代料（不在目录中）
KSZ9897RTXC-TR
✅ 直接替换📋 参考替代料（不在目录中）
KSZ9897RTXI-TR
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$9.2 / 个
查看数据手册 →KSZ9896CTXI
✅ 直接替换📋 参考替代料（不在目录中）
KSZ9477STXI
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
联系询价
查看数据手册 →KSZ9897RTXC 最大额定值与电气特性
| Product Type | Managed Layer-2 Ethernet Switch |
| Number of Ports | 7 (5 integrated PHYs + 2 configurable SGMII/RGMII/MII/RMII) |
| PHY Speed | 10/100/1000 Mbps (5 ports, Base-T) |
| Configurable Port Interfaces | SGMII, RGMII, MII, RMII |
| Management Interface | I2C and SPI |
| Supported Standards | IEEE 802.1Q VLAN, 802.1p QoS, 802.3az EEE, AVB/TSN timestamping |
| Wake-on-LAN | Supported |
| Supply Voltages | 1.8 V, 2.5 V, 3.3 V |
| 封装 | 128-pin TQFP-EP, 14x14 mm |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (per distributor listings) |
| Internal CPU / Management Engine | Integrated management CPU with register interface |
KSZ9897RTXC 引脚配置
| 引脚 1 | VDD_1V8 — 1.8 V core supply |
| 引脚 2 | VDD_2V5 — 2.5 V analog supply |
| 引脚 3 | VDD_3V3 — 3.3 V I/O supply |
| 引脚 4 | GND — Ground |
| 引脚 5 | RESET_N — Active-low hardware reset |
| 引脚 6 | INT_N — Active-low interrupt output |
| 引脚 7 | SDA — I2C data (management interface) |
| 引脚 8 | SCL — I2C clock (management interface) |
| 引脚 9 | SPI_CLK — SPI clock (alternate management interface) |
| 引脚 10 | SPI_MOSI — SPI master-out / slave-in |
| 引脚 11 | SPI_MISO — SPI master-in / slave-out |
| 引脚 12 | SPI_CS_N — SPI chip-select (active-low) |
| 引脚 13 | P1_D0P — Port 1 PHY1 pair D0 positive (Base-T) |
| 引脚 14 | P1_D0N — Port 1 PHY1 pair D0 negative |
| 引脚 15 | P1_D1P — Port 1 PHY1 pair D1 positive |
| 引脚 16 | P1_D1N — Port 1 PHY1 pair D1 negative |
| 引脚 17 | P1_D2P — Port 1 PHY1 pair D2 positive |
| 引脚 18 | P1_D2N — Port 1 PHY1 pair D2 negative |
| 引脚 19 | P1_D3P — Port 1 PHY1 pair D3 positive |
| 引脚 20 | P1_D3N — Port 1 PHY1 pair D3 negative |
| 引脚 21 | P2_D0P — Port 2 PHY2 pair D0 positive |
| 引脚 22 | P2_D0N — Port 2 PHY2 pair D0 negative |
| 引脚 23 | P2_D1P — Port 2 PHY2 pair D1 positive |
| 引脚 24 | P2_D1N — Port 2 PHY2 pair D1 negative |
| 引脚 25 | P2_D2P — Port 2 PHY2 pair D2 positive |
| 引脚 26 | P2_D2N — Port 2 PHY2 pair D2 negative |
| 引脚 27 | P2_D3P — Port 2 PHY2 pair D3 positive |
| 引脚 28 | P2_D3N — Port 2 PHY2 pair D3 negative |
| 引脚 29 | P3_D0P — Port 3 PHY3 pair D0 positive |
| 引脚 30 | P3_D0N — Port 3 PHY3 pair D0 negative |
| 引脚 31 | P3_D1P — Port 3 PHY3 pair D1 positive |
| 引脚 32 | P3_D1N — Port 3 PHY3 pair D1 negative |
| 引脚 33 | P3_D2P — Port 3 PHY3 pair D2 positive |
| 引脚 34 | P3_D2N — Port 3 PHY3 pair D2 negative |
| 引脚 35 | P3_D3P — Port 3 PHY3 pair D3 positive |
| 引脚 36 | P3_D3N — Port 3 PHY3 pair D3 negative |
| 引脚 37 | P4_D0P — Port 4 PHY4 pair D0 positive |
| 引脚 38 | P4_D0N — Port 4 PHY4 pair D0 negative |
| 引脚 39 | P4_D1P — Port 4 PHY4 pair D1 positive |
| 引脚 40 | P4_D1N — Port 4 PHY4 pair D1 negative |
| 引脚 41 | P4_D2P — Port 4 PHY4 pair D2 positive |
| 引脚 42 | P4_D2N — Port 4 PHY4 pair D2 negative |
| 引脚 43 | P4_D3P — Port 4 PHY4 pair D3 positive |
| 引脚 44 | P4_D3N — Port 4 PHY4 pair D3 negative |
| 引脚 45 | P5_D0P — Port 5 PHY5 pair D0 positive |
| 引脚 46 | P5_D0N — Port 5 PHY5 pair D0 negative |
| 引脚 47 | P5_D1P — Port 5 PHY5 pair D1 positive |
| 引脚 48 | P5_D1N — Port 5 PHY5 pair D1 negative |
| 引脚 49 | P5_D2P — Port 5 PHY5 pair D2 positive |
| 引脚 50 | P5_D2N — Port 5 PHY5 pair D2 negative |
| 引脚 51 | P5_D3P — Port 5 PHY5 pair D3 positive |
| 引脚 52 | P5_D3N — Port 5 PHY5 pair D3 negative |
| 引脚 53 | P6_TX_P — Port 6 (configurable) TX positive (RGMII/SGMII/MII/RMII) |
| 引脚 54 | P6_TX_N — Port 6 TX negative |
| 引脚 55 | P6_RX_P — Port 6 RX positive |
| 引脚 56 | P6_RX_N — Port 6 RX negative |
| 引脚 57 | P7_TX_P — Port 7 (configurable) TX positive |
| 引脚 58 | P7_TX_N — Port 7 TX negative |
| 引脚 59 | P7_RX_P — Port 7 RX positive |
| 引脚 60 | P7_RX_N — Port 7 RX negative |
| 引脚 61 | LED_PHY0_22G — Port 1 LED (link/activity/speed) |
| 引脚 62 | LED_PHY1_22G — Port 2 LED |
| 引脚 63 | LED_PHY2_22G — Port 3 LED |
| 引脚 64 | LED_PHY3_22G — Port 4 LED |
| 引脚 65 | LED_PHY4_22G — Port 5 LED |
| 引脚 66 | LED_P6 — Port 6 LED |
| 引脚 67 | LED_P7 — Port 7 LED |
| 引脚 68 | GPIO0 — General-purpose I/O 0 |
| 引脚 69 | GPIO1 — General-purpose I/O 1 |
| 引脚 70 | GPIO2 — General-purpose I/O 2 |
| 引脚 71 | GPIO3 — General-purpose I/O 3 |
| 引脚 72 | GPIO4 — General-purpose I/O 4 |
| 引脚 73 | GPIO5 — General-purpose I/O 5 |
| 引脚 74 | GPIO6 — General-purpose I/O 6 |
| 引脚 75 | GPIO7 — General-purpose I/O 7 |
| 引脚 76 | TX_CLK — Port 6/7 RGMII/MII transmit clock |
| 引脚 77 | RX_CLK — Port 6/7 RGMII/MII receive clock |
| 引脚 78 | TXD0 — RGMII/MII/RMII transmit data 0 |
| 引脚 79 | TXD1 — RGMII/MII/RMII transmit data 1 |
| 引脚 80 | TXD2 — RGMII transmit data 2 |
| 引脚 81 | TXD3 — RGMII transmit data 3 |
| 引脚 82 | TX_EN — Transmit enable |
| 引脚 83 | RXD0 — RGMII/MII/RMII receive data 0 |
| 引脚 84 | RXD1 — RGMII/MII/RMII receive data 1 |
| 引脚 85 | RXD2 — RGMII receive data 2 |
| 引脚 86 | RXD3 — RGMII receive data 3 |
| 引脚 87 | RX_DV — Receive data valid |
| 引脚 88 | CRS_DV — Carrier sense / data valid (MII/RMII) |
| 引脚 89 | MDC — Management data clock (PHY MIIM) |
| 引脚 90 | MDIO — Management data I/O (PHY MIIM) |
| 引脚 91 | REF_CLK — Reference clock input |
| 引脚 92 | VDD_1V8 — 1.8 V core supply |
| 引脚 93 | GND — Ground |
| 引脚 94 | TEST — Test mode (tie to strap-internal pull-down per datasheet) |
| 引脚 95 | NC — Not connected |
| 引脚 96 | NC — Not connected |
| 引脚 97 | VDD_3V3 — 3.3 V I/O supply |
| 引脚 98 | GND — Ground |
| 引脚 99 | P5_LED — Port 5 LED (alt mapping) |
| 引脚 100 | P4_LED — Port 4 LED (alt mapping) |
| 引脚 101 | P3_LED — Port 3 LED (alt mapping) |
| 引脚 102 | P2_LED — Port 2 LED (alt mapping) |
| 引脚 103 | P1_LED — Port 1 LED (alt mapping) |
| 引脚 104 | VDD_2V5 — 2.5 V analog supply |
| 引脚 105 | GND — Ground |
| 引脚 106 | NC — Not connected |
| 引脚 107 | NC — Not connected |
| 引脚 108 | JTAG_TCK — JTAG test clock |
| 引脚 109 | JTAG_TMS — JTAG test mode select |
| 引脚 110 | JTAG_TDI — JTAG test data in |
| 引脚 111 | JTAG_TDO — JTAG test data out |
| 引脚 112 | JTAG_TRST_N — JTAG test reset (active-low) |
| 引脚 113 | VDD_1V8 — 1.8 V core supply |
| 引脚 114 | GND — Ground |
| 引脚 115 | NC — Not connected |
| 引脚 116 | NC — Not connected |
| 引脚 117 | P6_SGMII_REF — Port 6 SGMII reference clock |
| 引脚 118 | P7_SGMII_REF — Port 7 SGMII reference clock |
| 引脚 119 | VDD_3V3 — 3.3 V I/O supply |
| 引脚 120 | GND — Ground |
| 引脚 121 | NC — Not connected |
| 引脚 122 | NC — Not connected |
| 引脚 123 | P6_LED_LINK — Port 6 link LED |
| 引脚 124 | P7_LED_LINK — Port 7 link LED |
| 引脚 125 | VDD_1V8 — 1.8 V core supply |
| 引脚 126 | GND — Ground |
| 引脚 127 | NC — Not connected |
| 引脚 128 | NC — Not connected |
典型应用
KSZ9897RTXC 适用于 7 应用s: Industrial Gigabit Ethernet Switch, IP Surveillance / NVR Backbone, Automotive Infotainment Backbone, Smart-Grid / Energy Gateway, IoT Edge Router / Smart-Home Hub, Pro-AV / Broadcast Video Bridge, Industrial IoT Gateway / Edge Compute.
Industrial Gigabit Ethernet Switch
The KSZ9897RTXC fits industrial managed Gigabit switches because it provides seven ports (five integrated 10/100/1000 PHYs plus two configurable SGMII/RGMII/MII/RMII uplinks) on a single die, eliminating the need for an external PHY stack. With hardware-based wire-speed ACL/QoS and 14 Gbps of switching capacity, it handles full line-rate traffic across all ports simultaneously. The exposed thermal pad on the 128-pin TQFP-EP package conducts heat to the PCB copper plane, supporting fanless industrial enclosures. Pair with the KSZ9897RTXI variant when the cabinet sits in an uncontrolled-temperature environment.
推荐
IP Surveillance / NVR Backbone
IP-camera NVRs and surveillance recorders benefit from the KSZ9897RTXC's five integrated Gigabit PHYs, which connect directly to multiple 4K IP cameras without an external PHY stack. Hardware ACL/QoS engines prioritize video streams over management packets, preserving bandwidth for critical recording traffic. Wake-on-LAN reduces idle power consumption when no motion is detected. The two configurable SGMII/RGMII ports provide uplink to a host SoC or a second switch tier for cascaded storage arrays.
推荐
Automotive Infotainment Backbone
In automotive head units and infotainment controllers, the KSZ9897RTXC delivers AVB/TSN timestamping required for synchronized audio/video streams to multiple displays. Five Base-T PHYs connect to telematics, camera modules, rear-seat entertainment, and diagnostic ports; the two configurable MAC ports connect to the application processor and an automotive Ethernet PHY. The 14 Gbps capacity easily manages back-to-back design where up to 7 networked devices share a single switch. Choose KSZ9897RTXI when the cabin temperature envelope exceeds commercial grade.
推荐
Smart-Grid / Energy Gateway
Smart-grid gateways and energy-management controllers use the KSZ9897RTXC to aggregate multiple HAN/BAN segments over Gigabit Ethernet while maintaining strict QoS for control traffic. Hardware ACLs segment meter data, demand-response signals, and management traffic into separate VLANs, isolating critical SCADA communications. Wake-on-LAN keeps idle field gateways in low-power states. The integrated management CPU simplifies firmware design by removing the requirement for an external host MCU.
推荐
IoT Edge Router / Smart-Home Hub
IoT edge routers and smart-home hubs require multiple Gigabit ports to bridge Wi-Fi, Thread/Zigbee gateways, and downstream IoT devices to the WAN. The KSZ9897RTXC's five integrated PHYs handle LAN-side devices, while the configurable SGMII/RGMII port connects to a Wi-Fi 6/Wi-Fi 7 SoC such as IPQ8072. IEEE 802.3az Energy Efficient Ethernet plus Wake-on-LAN reduce idle power when no LAN traffic flows, a key requirement for always-on Smart Home devices.
推荐
Pro-AV / Broadcast Video Bridge
Pro-AV video walls and broadcast bridging equipment benefit from the KSZ9897RTXC's AVB/TSN timestamping for sample-accurate video synchronization across multiple endpoints. Five integrated PHYs drive video-source/distributor faces with no cluster-level latency; the configurable MAC ports feed a video processor or an SDI/IP bridge. Wire-speed non-blocking switching guarantees that 4K/8K video streams never drop frames, even when the device sits in a 7-port cluster. Hardware QoS tagging preserves time-sensitive isochronous streams.
推荐
Industrial IoT Gateway / Edge Compute
Industrial IoT gateways aggregate field-bus segments (Modbus TCP, EtherNet/IP, PROFINET) over multiple Gigabit uplinks. The KSZ9897RTXC's hardware ACLs isolate each protocol into its own VLAN while preserving line-rate forwarding. Wake-on-LAN keeps field-deployed gateways in sleep mode until sensors trigger traffic, conserving battery and reducing operating expense. The integrated management CPU removes the requirement for an external switch controller, shrinking BOM cost and PCB area for space-constrained designs.
推荐
推荐产品汇总
工程参考数据： KSZ9897RTXC ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | KSZ9897RTXI | KSZ9897RTXC-TR | KSZ9897RTXI-TR | KSZ9896CTXI | KSZ9477STXI |
|---|---|---|---|---|---|---|
| Package | 128-pin TQFP-EP (14x14 mm) | 128-pin TQFP-EP (14x14 mm) - same | 128-pin TQFP-EP (14x14 mm) - same | 128-pin TQFP-EP (14x14 mm) - same | 128-pin TQFP-EP (14x14 mm) - same | 128-pin TQFP-EP (14x14 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Number of Ports | 7 (5 integrated PHYs + 2 configurable) | 7 (identical) | 7 (identical) | 7 (identical) | 6 (one fewer integrated PHY, ~14% fewer ports) | 7 (adds fiber SGMII/SERDES) |
| Integrated Gigabit PHYs | 5 | 5 (identical) | 5 (identical) | 5 (identical) | 6 (one more than KSZ9897) | 5 + SERDES (different mix) |
| Temperature Grade | Commercial (0 to 70 C) | Industrial (-40 to +85 C) | Commercial (identical) | Industrial (-40 to +85 C) | Industrial (-40 to +85 C) | Industrial (-40 to +85 C) |
| Switching Capacity | 14 Gbps non-blocking | 14 Gbps (identical) | 14 Gbps (identical) | 14 Gbps (identical) | 12 Gbps (~14% lower) | 14 Gbps (identical) |
| Management Interface | I2C, SPI, MIIM | I2C, SPI, MIIM (identical) | I2C, SPI, MIIM (identical) | I2C, SPI, MIIM (identical) | I2C, SPI, MIIM (identical) | I2C, SPI, MIIM (identical) |
| AVB/TSN Support | Yes | Yes (identical) | Yes (identical) | Yes (identical) | Yes | Yes (extended) |
| Approx. Unit Price (qty 1) | $14.50 | $15.80 (industrial premium ~9%) | $14.50 (tape-and-reel, identical) | $15.80 (industrial + T&R) | $12.95 (~11% lower) | $17.20 (~19% higher) |
关键差异点
- Seven ports with five integrated Gigabit PHYs in a single 128-pin TQFP-EP package （对比 KSZ9896CTXI)
- Hardware-based wire-speed ACL/QoS engines （对比 KSZ9477STXI)
- AVB/TSN timestamping integrated on-chip （对比 KSZ8995MAI)
设计说明
The 128-pin TQFP-EP package provides an exposed thermal pad on the underside that MUST be soldered to a sufficiently large copper ground plane (recommend at least 1 square inch of 2 oz copper) to keep junction temperature within the operating envelope. Estimated: with seven Gigabit ports active at full line-rate traffic, the part dissipates approximately 1.5-2.0 W; without an adequate thermal pad, theta_JA is high enough to exceed thermal limits in sealed enclosures. Use thermal vias under the EP per Microchip's recommended PCB footprint.
Route the 1000BASE-T differential pairs (P1-P5) with 100-ohm differential impedance and match intra-pair length to within 5 mils; pair-to-pair matching should be within 25 mils to keep skew within IEEE 802.3 tolerances. Keep the 5 integrated PHY traces on layer 4 over a continuous ground reference plane and minimize vias. Decouple each VDD rail (1.8 V, 2.5 V, 3.3 V) with 100 nF ceramic capacitors placed within 100 mils of the supply pins and a bulk 10 uF tantalum or capacitor per network.
The two configurable ports (P6, P7) support SGMII, RGMII, MII, or RMII depending on strap or strapping resistors at reset. For SGMII operation the trace length should be kept under 4 inches with 100-ohm differential impedance; RGMII traces should match source-synchronous clock-to-data length within 50 mils. For MIIM/MDC/MDIO the MDC clock should be kept under 25 MHz to meet setup/hold timing. Refer to the KSZ9897 family datasheet section covering PHY configuration for strap options.
Do not leave the I/M/I pins (MUM) floating - strap them per the KSZ9897 family datasheet strap table at reset to select the desired configuration (port count, AVB enable, EEE enable, etc.). Failing to strap these pins correctly can leave the part in an undefined state where some ports do not link. Also verify the SPI/I2C mode strap before firmware initialization; using both SPI and I2C concurrently is not allowed and will cause bus contention.
合规信息
RoHS and REACH compliance per DigiKey and Mouser distributor listings. AEC-Q100 verified industrial-grade KSZ9897RTXI is available separately; this AEC-Q100 verification is not applicable to the standard KSZ9897RTXC. Halogen-free status is verified per datasheet. Conflict-minerals verified compliant per Microchip product stewardship.
