LTC2175CUKG-14 - 14-Bit 125Msps Quad ADC | Analog Devices
料号： LTC2175CUKG-14 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $95.1 | $95.10 |
| 10 | $85.6 | $856.00 |
| 100 | $76.2 | $7,620.00 |
| 500 | $68.5 | $34,250.00 |
| 1,000 | $60.7 | $60,700.00 |
LTC2175CUKG-14 概述
A pipelined ADC is a multi-stage converter architecture that uses successive low-resolution flash stages and digital correction to achieve high sample rates while keeping per-stage comparator count and power consumption low compared to a full-flash converter. The LTC2175 family sits in the broader taxonomy of Nyquist-rate ADCs, distinguishing from successive-approximation register (SAR) and delta-sigma ADCs by its high sampling rate and moderate per-channel latency. Within the signal chain, the quad-channel integration reduces board area for parallel-channel systems such as multi-antenna receivers or quadrature IF sampling.
Key specifications include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes across the operating temperature range, and 1.2 LSB RMS transition noise. Each channel supports two LVDS output lanes by default, with a one-bit-per-channel mode configurable at lower sampling rates. The serial LVDS interface minimizes the number of board data traces, simplifying PCB routing in dense multi-channel designs.
The device is optimized for low power consumption, with most thermal dissipation transferred through the bottom-side exposed pad onto the PCB copper. Designers should follow the recommended PCB layout for the exposed pad and provide adequate ground and supply decoupling around each analog input pin. The combination of four channels, 14-bit resolution, and 125 Msps sampling rate makes the LTC2175CUKG-14 well suited to communications infrastructure, multi-antenna diversity receivers, I/Q baseband sampling, and portable test instrumentation.
When integrating this ADC, ensure that the analog inputs are AC- or DC-coupled through properly sized transformer or driver networks, that the sample clock has low jitter for SNR preservation, and that the LVDS output lanes are length-matched with controlled impedance. The exposed pad must be soldered to a sufficient copper pour to keep junction temperature within the derated limit at maximum sample rate and ambient.
This page synthesizes distributor availability, drop-in same-family alternatives, and PCB-level design notes that go beyond the manufacturer datasheet to assist engineers evaluating the LTC2175CUKG-14 for next-generation multi-channel receiver or instrumentation designs.
直接替换替代料： LTC2175CUKG-14 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2175CUKG-14 （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature Range, Input Type, Resolution, Digital Output Interface.
快速对比工具——选择替代料号进行并排对比：
LTC2175IUKG-14
✅ 直接替换📋 参考替代料（不在目录中）
LTC2175CUKG-14#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2175CUKG-14#TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2174CUKG-14
✅ 直接替换✓ 有现货
$48.9 / 个
查看数据手册 →LTC2171CUKG-14
✅ 直接替换✓ 有现货
$26.75 / 个
查看数据手册 →LTC2173CUKG-14
✅ 直接替换📋 参考替代料（不在目录中）
LTC2175CUKG-14 最大额定值与电气特性
| Manufacturer | Analog Devices (formerly Linear Technology) |
| Part Number | LTC2175CUKG-14 |
| Number of Bits | 14 |
| Number of Inputs / Channels | 4 |
| 采样率 | 125 Msps per channel |
| Architecture | Pipelined |
| Input Type | Differential (per datasheet) |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Missing Codes | No missing codes over temperature |
| Transition Noise | 1.2 LSB RMS |
| Digital Output Interface | Serial LVDS (2-lane and 1-lane modes) |
| 封装 | 52-QFN (7mm x 8mm) with exposed pad |
| 引脚数量 | 52 |
| 安装类型 | Surface Mount |
| Temperature Grade | Commercial (0C to +70C) per 'C' in part marking |
| Lead Finish | Lead-free (#PBF) |
| RoHS 状态 | Compliant per #PBF suffix |
LTC2175CUKG-14 52-qfn (7mm x 8mm) with exposed pad 引脚配置指南
LTC2175CUKG-14（52-qfn (7mm x 8mm) with exposed pad 封装）的引脚配置。 该模拟元件具有输入、输出和电源引脚。请参阅制造商数据手册以了解失调调零、补偿和使能引脚配置。适用于信号调理和放大器电路。
暂无详细引脚数据： LTC2175CUKG-14.
请参阅 数据手册 以查看完整引脚配置。
典型应用
LTC2175CUKG-14 适用于 7 应用s: Multi-Antenna MIMO and Phased-Array Receivers, Quadrature I/Q Baseband Sampling in Software-Defined Radio, Portable Test and Measurement Instrumentation, Medical Imaging and Ultrasound Front-Ends, Radar and Lidar Signal Digitization, Wireless Infrastructure Baseband Processing, Industrial Data Acquisition Systems.
Multi-Antenna MIMO and Phased-Array Receivers
The LTC2175CUKG-14 integrates four simultaneously-sampling 14-bit ADC channels at 125 Msps in a single 52-QFN (UKG) footprint, eliminating inter-channel sampling skew at the silicon level. This is critical for MIMO (multiple-input multiple-output) and phased-array receivers in 4G/5G base-station baseband, where the relative timing of four antenna streams must be preserved for channel estimation and beamforming. The 14-bit resolution provides 84 dB ideal dynamic range, sufficient for demodulating QAM-16/64/256 constellations, while the serialized LVDS output reduces trace congestion when routing four channels to an FPGA. At 125 Msps, the part can undersample IF bands used in digital-IF receiver architectures up to ~62 MHz carrier frequency. Reference analog front-ends pair this ADC with the Analog Devices ADL5201 gain stage and HMCAD1512 clock distribution for full multi-channel receive chains.
推荐
Quadrature I/Q Baseband Sampling in Software-Defined Radio
The four-channel integration of the LTC2175CUKG-14 maps naturally onto the I and Q pairs from two independent receivers in a software-defined radio (SDR) front-end, allowing complete baseband digitization of dual-channel radios in a single IC. Each channel's 125 Msps rate supports baseband bandwidths up to ~62 MHz, sufficient for LTE signals up to 20 MHz and Wi-Fi 802.11ac channels up to 80 MHz when paired with appropriate decimation. The serial LVDS interface is favored for SDR designs because it routes data efficiently into the FPGA's SERDES blocks. Combined with the Analog Devices AD9361 RF front-end or similar integrated transceivers, the LTC2175CUKG-14 forms the ADC half of a direct-conversion receiver chain. The pipelined architecture's low latency (~few clock cycles) is well suited to real-time signal processing pipelines where latency budget is constrained.
推荐
Portable Test and Measurement Instrumentation
Portable oscilloscope, spectrum analyzer, and arbitrary waveform digitizer designs benefit from the LTC2175CUKG-14's quad-channel integration at 14-bit/125 Msps, reducing board area and BOM cost. The low-power design emphasizes efficiency, extending battery life in handheld or USB-powered test instruments where four ADC channels digitize trigger, time-base, and measurement channels concurrently. The 1.2 LSB RMS transition noise floor yields ~74 dB effective number of bits (ENOB) under typical conditions, adequate for general-purpose instrumentation dynamic range. The exposed thermal pad keeps the junction temperature within derated limits in space-constrained instruments without an internal fan. Designers typically pair this ADC with an FPGA for inline trigger logic and a downstream DDR memory for deep capture.
推荐
Medical Imaging and Ultrasound Front-Ends
The LTC2175CUKG-14's four simultaneous-sampling channels suit medical ultrasound beamforming front-ends where each transducer element or sub-array tap requires an independent digitizer at tens to hundreds of Msps. The 14-bit dynamic range ensures adequate gray-scale resolution for diagnostic-grade imaging, while the pipelined architecture's deterministic latency keeps beamformer calculations coherent across channels. The serial LVDS output simplifies routing the many parallel data streams out to a central processing FPGA in densely-populated ultrasound carts. The commercial temperature grade is suitable for use in environmentally controlled hospital rooms; for portable bedside ultrasound, consider the LTC2175IUKG-14 industrial variant for wider thermal tolerance.
推荐
Radar and Lidar Signal Digitization
Automotive and industrial radar, as well as time-of-flight lidar receiver chains, leverage the LTC2175CUKG-14's simultaneously-sampling quad channel at 125 Msps to digitize I/Q channels from two or four mixer outputs directly at the IF or baseband. The pipelined converter's clean ±1 LSB INL preserves phase accuracy across the receive beamforming and angle-of-arrival estimation, while the high sampling rate supports GHz-class IF subsampling with the analog input bandwidth extending well beyond 100 MHz. The 52-QFN 7x8 mm footprint integrates a complete multi-channel digital IF section into a compact PCB footprint, fitting easily behind the antenna array or onto a lidar sensor PCB. Designs pairing the ADC with FMCW chirp generation and phase-locked loop timing (e.g., Analog Devices ADF41020) realize full radar front-ends.
推荐
Wireless Infrastructure Baseband Processing
The LTC2175CUKG-14 provides the digitizer stage for cellular base-station baseband processing, where multiple carriers and antenna streams must be sampled simultaneously for the digital front-end to perform digital up/down-conversion, channelization, and crest-factor reduction. At 125 Msps per channel, the part supports direct baseband and low-IF sampling for carriers up to ~60 MHz wide, easily accommodating multiband LTE and 5G NR configurations. The serialized LVDS interface minimizes the number of PCB data lines crossing between the RF front-end and the FPGA processor, reducing the card's high-speed trace count. Paired with the Analog Devices ADRF6820 wideband I/Q demodulator, the ADC completes a robust multi-channel receiver card. Designers should follow the datasheet's recommended PCB layout for the exposed pad to ensure thermal performance.
推荐
Industrial Data Acquisition Systems
Multi-sensor data acquisition systems in factory automation, vibration monitoring, and condition-monitoring equipment frequently require four synchronized analog inputs at tens of Msps per channel. The LTC2175CUKG-14's four synchronous channels, 125 Msps per channel, and 14-bit resolution offer the throughput and dynamic range needed for vibration spectral analysis, modal testing, and rotating-machinery predictive maintenance. The lead-free (#PBF) finish supports industrial RoHS-compliant build requirements, while the LVDS interface avoids crosstalk concerns in noisy factory environments. Typical designs combine the ADC with anti-aliasing filters, front-end signal conditioning, and an FPGA performing real-time FFT.
推荐
推荐产品汇总
工程参考数据： LTC2175CUKG-14 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2175IUKG-14 | LTC2175CUKG-14#PBF | LTC2175CUKG-14#TRPBF | LTC2174CUKG-14 | LTC2171CUKG-14 | LTC2173CUKG-14 |
|---|---|---|---|---|---|---|---|
| Package | 52-QFN (UKG, 7x8 mm) | 52-QFN (UKG, 7x8 mm) - same footprint | 52-QFN (UKG, 7x8 mm) - same footprint | 52-QFN (UKG, 7x8 mm) - same footprint | 52-QFN (UKG, 7x8 mm) - same footprint | 52-QFN (UKG, 7x8 mm) - same footprint | 52-QFN (UKG, 7x8 mm) - same footprint |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Number of Bits | 14 | 14 | 14 | 14 | 14 | 14 | 14 |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
| Sampling Rate (Msps) | 125 | 125 | 125 | 125 | 105 | 105 | 80 |
| Temperature Grade | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Lead-Free / RoHS | Yes (#PBF) | Yes | Yes | Yes | Yes | Yes | Yes |
| Digital Output Interface | Serial LVDS (2-lane / 1-lane) | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
关键差异点
- Quad-channel simultaneous sampling in a single 52-QFN footprint at 125 Msps per channel （对比 LTC2156IUP-14 (Site MPN))
- Serial LVDS interface reduces board trace count vs parallel CMOS alternatives （对比 LTC2172IUKG-12 (Site MPN))
- 125 Msps headroom over 105 Msps siblings in the same 52-QFN (UKG) footprint （对比 LTC2171CUKG-14 (Site MPN))
- Drop-in compatibility with industrial-temperature sibling （对比 LTC2175IUKG-14)
设计说明
Always solder the exposed thermal pad on the underside of the 52-QFN (UKG) package to a continuous, low-impedance PCB ground plane to maintain junction temperature within derated limits. The LTC2175CUKG-14 datasheet (21754314fa) explicitly notes that 'most of the heat generated by the LTC2175-14/LTC2174-14/LTC2173-14 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board'. Insufficient thermal contact causes overheating at 125 Msps in commercial temperature applications. Use multiple thermal vias directly under the pad and avoid thermal reliefs on those pads so the PCB's copper pour acts as a heatsink.
Route the LVDS output lanes between the LTC2175CUKG-14 and the receiving FPGA as length-matched, impedance-controlled differential pairs (typically 100 ohm differential) and avoid stubs or 90-degree bends. Each lane pair should be length-matched within a few millimetres to keep inter-channel skew as small as possible. Reference the datasheet's typical application circuit for the recommended termination and coupling capacitor placements at the FPGA receiver inputs. Keep LVDS data lines away from the analog input traces and clock distribution networks to prevent coupling of digital switching noise into the analog front-end.
Estimate: at 125 Msps with full-scale input, the dynamic performance of the LTC2175CUKG-14 is governed by sample-clock jitter, not by ADC aperture uncertainty, once clock jitter falls below roughly 1 ps RMS. Therefore use a low-jitter clock source (e.g., a dedicated jitter cleaner such as the Analog Devices AD9516 or HMCAD1050 from the Site MPN list) rather than spreading the FPGA's internal PLL output. For each additional picosecond of clock jitter, expect roughly 0.7 dB drop in SNR at full-scale analog input per the standard SNR_jitter = 20 log10 (1 / (2 pi f_in sigma_jitter)) relationship. Drive the analog inputs differentially through a balun or low-noise ADC driver such as the LT6203 to preserve SFDR.
Estimated: at 125 Msps per channel and four channels active, the LTC2175CUKG-14 analog and digital supply rails draw roughly 200-300 mA total depending on output-mode configuration (verified detailed current budget is left to the datasheet which lists per-supply typical values). Provide local 0.1 uF + 10 uF ceramic decoupling at each supply pin, with the lowest-impedance 0.1 uF placed closest to the pin. Use a ferrite-bead or pi-filter separation between the analog and digital supply domains to prevent digital switching noise from coupling into the analog front-end, which would otherwise degrade SNR and SFDR.
Estimated: at 125 Msps continuous operation across four channels, total power dissipation can reach 700-900 mW (datasheet figure is required for verification - consult the datasheet's Electrical Characteristics table for VDD_I/O at the intended supply voltages). On a standard JEDEC EIA/JESD51 4-layer PCB with reasonable copper pour, the 52-QFN (UKG) junction-to-ambient thermal resistance is approximately 25-30 C/W, implying a 20-27 C temperature rise above ambient. For commercial 0C to +70C operation, this is easily within margins; if the application targets higher ambient temperatures, derate by reducing sample rate or by upgrading the PCB thermal design.
合规信息
#PBF suffix indicates RoHS-compliant lead-free finish per Linear Technology / Analog Devices ordering convention. AEC-Q100 not applicable - this is a commercial-temperature-grade ADC for non-automotive use. Halogen-free status not explicitly stated in retrieved web data.
