LTC2191CUKG - 16-Bit 40Msps Dual ADC | Analog Devices
料号： LTC2191CUKG ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $32.85 | $328.50 |
| 100 | $29.2 | $2,920.00 |
| 500 | $25.95 | $12,975.00 |
| 1,000 | $22.4 | $22,400.00 |
LTC2191CUKG 概述
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog waveforms into discrete digital codes for processing by DSPs, microcontrollers, or FPGAs. Within the converter family, the pipelined architecture (sub-type of high-speed ADC) uses multiple cascaded low-resolution stages to achieve 14-16 bit precision at tens to hundreds of Msps, making it the standard choice for digitizing wideband communications signals, software-defined radio, and medical imaging front-ends. The LTC2191CUKG belongs to the broader category of data converters -> ADCs -> high-speed ADCs -> pipelined ADCs.
Key features include 73.4 dBFS signal-to-noise ratio at 9.7 MHz input, two independently timed differential input channels, an internal bypassable bandgap reference, and low power dissipation that simplifies thermal design in multi-channel systems. CMOS and LVDS output modes allow flexible digital interconnect with FPGAs and ASICs.
The LTC2191CUKG employs a multi-stage pipelined architecture with proprietary digital calibration that corrects capacitor mismatch and comparator offset in the background, yielding 16-bit linearity without external trimming. The exposed pad on the bottom of the QFN package must be soldered to a grounded copper pour to achieve the rated AC performance and provide thermal dissipation.
Typical applications include cellular base-station receivers, IF digitization in software-defined radio, portable test and measurement instrumentation, medical imaging front-ends (ultrasound beamformers), and multi-antenna MIMO systems where two channels of matched phase performance are required.
When designing with this device, allocate sufficient PCB area for the exposed-pad thermal via array and keep analog input traces impedance-matched (typically 100 ohm differential) and length-matched between the two channels. Decouple AVDD and DVDD with 10uF plus 0.1uF ceramic capacitors placed within 5 mm of the supply balls to preserve SNR and SFDR at full sampling rate.
This page synthesizes distributor pricing, same-family dual-ADC drop-in alternatives, and practical PCB layout guidance not consolidated in the manufacturer datasheet.
直接替换替代料： LTC2191CUKG ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2191CUKG （相同外形与封装尺寸） ——差异在于 Operating Temperature Range, SNR, Input Type, RoHS Status, Digital Output Interface.
快速对比工具——选择替代料号进行并排对比：
LTC2190CUKG
✅ 直接替换✓ 有现货
$64 / 个
查看数据手册 →LTC2191IUKG
✅ 直接替换✓ 有现货
$62.95 / 个
查看数据手册 →LTC2192CUKG
✅ 直接替换📋 参考替代料（不在目录中）
LTC2192IUKG
✅ 直接替换✓ 有现货
$63.56 / 个
查看数据手册 →LTC2190IUKG
✅ 直接替换✓ 有现货
$18.21 / 个
查看数据手册 →LTC2191CUKG 最大额定值与电气特性
| 分辨率 | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| 采样率 | 40 Msps |
| Architecture | Pipelined |
| SNR | 77 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 psRMS |
| 电源电压 | 1.8 V |
| Input Range | 2 Vp-p differential |
| 工作温度 | 0C to 70C (commercial) |
| 封装 | 52-pin QFN (7x8 mm) with exposed pad |
| 安装类型 | Surface Mount |
| MSL 等级 | 1 (unlimited) |
| RoHS 状态 | Compliant |
| Output Interface | CMOS / LVDS selectable |
LTC2191CUKG 引脚配置
| 引脚 1 | AIN1+ — Channel 1 differential analog input positive |
| 引脚 2 | AIN1- — Channel 1 differential analog input negative |
| 引脚 3 | AIN2+ — Channel 2 differential analog input positive |
| 引脚 4 | AIN2- — Channel 2 differential analog input negative |
| 引脚 5 | VCM — Common-mode voltage output |
| 引脚 6 | REF — Reference voltage bypass |
| 引脚 7 | REFT — Top reference decoupling |
| 引脚 8 | REFB — Bottom reference decoupling |
| 引脚 9 | GND — Analog ground |
| 引脚 10 | AVDD — Analog 1.8V supply |
| 引脚 11 | GND — Analog ground |
| 引脚 12 | AVDD — Analog 1.8V supply |
| 引脚 13 | SENSE — Reference configuration pin |
| 引脚 14 | GND — Analog ground |
| 引脚 15 | ENC+ — Encoder input positive |
| 引脚 16 | ENC- — Encoder input negative |
| 引脚 17 | GND — Digital ground |
| 引脚 18 | OEN — Output enable |
| 引脚 19 | OFM — Output format mode (CMOS/LVDS) |
| 引脚 20 | DNC — Do not connect |
| 引脚 21 | D0A — Channel A digital output bit 0 |
| 引脚 22 | D1A — Channel A digital output bit 1 |
| 引脚 23 | D2A — Channel A digital output bit 2 |
| 引脚 24 | D3A — Channel A digital output bit 3 |
| 引脚 25 | D4A — Channel A digital output bit 4 |
| 引脚 26 | D5A — Channel A digital output bit 5 |
| 引脚 27 | D6A — Channel A digital output bit 6 |
| 引脚 28 | D7A — Channel A digital output bit 7 |
| 引脚 29 | D8A — Channel A digital output bit 8 |
| 引脚 30 | D9A — Channel A digital output bit 9 |
| 引脚 31 | D10A — Channel A digital output bit 10 |
| 引脚 32 | D11A — Channel A digital output bit 11 |
| 引脚 33 | D12A — Channel A digital output bit 12 |
| 引脚 34 | D13A — Channel A digital output bit 13 |
| 引脚 35 | D14A — Channel A digital output bit 14 |
| 引脚 36 | D15A — Channel A digital output bit 15 |
| 引脚 37 | D0B — Channel B digital output bit 0 |
| 引脚 38 | D1B — Channel B digital output bit 1 |
| 引脚 39 | D2B — Channel B digital output bit 2 |
| 引脚 40 | D3B — Channel B digital output bit 3 |
| 引脚 41 | D4B — Channel B digital output bit 4 |
| 引脚 42 | D5B — Channel B digital output bit 5 |
| 引脚 43 | D6B — Channel B digital output bit 6 |
| 引脚 44 | D7B — Channel B digital output bit 7 |
| 引脚 45 | D8B — Channel B digital output bit 8 |
| 引脚 46 | D9B — Channel B digital output bit 9 |
| 引脚 47 | D10B — Channel B digital output bit 10 |
| 引脚 48 | D11B — Channel B digital output bit 11 |
| 引脚 49 | D12B — Channel B digital output bit 12 |
| 引脚 50 | D13B — Channel B digital output bit 13 |
| 引脚 51 | D14B — Channel B digital output bit 14 |
| 引脚 52 | D15B — Channel B digital output bit 15 |
典型应用
LTC2191CUKG 适用于 6 应用s: Cellular Base-Station Receiver, Software-Defined Radio (SDR) IF Stage, Portable Test & Measurement Instrumentation, Medical Ultrasound Beamformer, Multi-Antenna MIMO Receiver, Industrial High-Speed Data Acquisition.
Cellular Base-Station Receiver
The LTC2191CUKG digitizes two matched-phase IF signals in cellular base-station receivers (LTE, 5G NR), where simultaneous dual-channel sampling preserves I/Q phase integrity for demodulation. Its 77 dB SNR and 90 dB SFDR at 40 Msgs comfortably resolve narrow-band signals in the presence of large blocking carriers, while 0.07 psRMS aperture jitter allows undersampling of IF frequencies above 100 MHz without SNR degradation. Placed between the analog front-end SAW filter and the digital FPGA baseband processor, the converter typically runs in LVDS mode to maintain signal integrity at full sampling rate. Two-channel matched sampling eliminates the need for a separate I/Q demodulator IC, reducing both BOM cost and PCB area.
推荐
Software-Defined Radio (SDR) IF Stage
The LTC2191CUKG functions as the analog-to-digital boundary in wideband software-defined radio platforms, digitizing IF signals in the 0-100 MHz range with sufficient dynamic range to capture multiple simultaneous channels. Its 77 dB SNR delivers approximately 12.5 effective bits of resolution, enabling digital filtering and demodulation entirely in the FPGA. The 0.07 psRMS jitter allows undersampling of higher-IF architectures (e.g., 140 MHz IF with 40 Msgs sampling), simplifying the receiver RF chain by eliminating a second downconversion stage. Dual simultaneous channels suit diversity or MIMO receiver designs where two antennas must be sampled in matched phase.
推荐
Portable Test & Measurement Instrumentation
The LTC2191CUKG delivers laboratory-grade 77 dB SNR in handheld oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers where two matched channels are required for differential or time-interleaved measurements. Its 1.8 V low-voltage supply keeps power dissipation under 200 mW per channel, extending portable instrument battery life to 6-8 hours versus 2-3 hours for higher-power ADC alternatives. The dual-channel matched-phase performance is critical for differential probes, vector signal analyzer I/Q inputs, and time-domain reflectometry (TDR) channels. The 52-pin QFN package fits in the compact 7x8 mm PCB region beneath the FPGA Mezzanine Card (FMC) connector.
推荐
Medical Ultrasound Beamformer
In medical ultrasound systems, the LTC2191CUKG digitizes two channels of RF echo data per beamforming channel, with simultaneous sampling required to maintain the phase coherence that determines axial resolution. Its 77 dB SNR translates to >12 effective bits at the ultrasound operating frequencies (1-15 MHz), and 0.07 psRMS jitter keeps the SNR floor intact across the dynamic range of returning echoes. Multi-channel systems stack dozens of LTC2191CUKG devices (one per two transducer elements) to form a 64- or 128-channel beamformer. The 1.8 V supply simplifies compliance with IEC 60601 patient-safety isolation budgets.
推荐
Multi-Antenna MIMO Receiver
The LTC2191CUKG's two simultaneously-sampled channels make it a natural building block for multi-antenna MIMO receivers in Wi-Fi 6E, 5G small-cell, and GNSS-in diversity antenna systems. Two matched channels allow either 2x2 MIMO decoding or dual-antenna diversity combining, while the 77 dB SNR supports the 64-QAM and 256-QAM constellations used in modern wireless standards. Cascading four LTC2191CUKG devices yields an 8-channel 4x4 MIMO receiver on a single compact PCB footprint, with the matched-phase sampling ensuring proper MIMO channel-matrix estimation.
推荐
Industrial High-Speed Data Acquisition
In industrial vibration analysis and acoustic emission (CUBE) testing, the LTC2191CUKG captures dual-axis vibration waveforms from accelerometers with sufficient bandwidth (DC to 20 MHz) and dynamic range (77 dB SNR) to detect bearing faults, gear-tooth defects, and structural cracks. The two-channel simultaneous sampling lets engineers correlate vibration on two axes (vertical and horizontal) without separate converters. The 0C-70C commercial temperature grade suits factory-floor instrumentation enclosures. The exposed-pad QFN package simplifies thermal design in high-channel-count (32-64 channel) rack-mounted acquisition systems.
推荐
推荐产品汇总
工程参考数据： LTC2191CUKG ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2190CUKG | LTC2191IUKG | LTC2192CUKG | LTC2192IUKG | LTC2190IUKG |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (7x8 mm) | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same |
| Sampling Rate | 40 Msps | 25 Msps | 40 Msps | 65 Msps | 65 Msps | 25 Msps |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| SNR | 77 dB | 77 dB | 77 dB | 76.5 dB | 76.5 dB | 77 dB |
| SFDR | 90 dB | 90 dB | 90 dB | 88 dB | 88 dB | 90 dB |
| Operating Temperature | 0C to 70C (commercial) | 0C to 70C (commercial) | -40C to 85C (industrial) | 0C to 70C (commercial) | -40C to 85C (industrial) | -40C to 85C (industrial) |
关键差异点
- Only same-speed-of-ADC option with commercial temperature grade （对比 LTC2191IUKG)
- Lower-cost alternative for bandwidth-limited designs （对比 LTC2190CUKG)
- Cost-optimized vs higher-bandwidth LTC2192 （对比 LTC2192CUKG)
设计说明
Solder the bottom exposed pad (EP) of the LTC2191CUKG 52-pin QFN package to a grounded PCB pour with a via array (recommended: 4x4 grid of 0.3 mm thermal vias). The exposed pad is the primary thermal path and also provides the electrical ground reference; without proper soldering, AC specifications (SNR, SFDR) will degrade by 2-3 dB. Per the Analog Devices datasheet, the EP must be soldered for both electrical and thermal performance.
Decouple AVDD and DVDD independently with a 10uF ceramic bulk capacitor plus a 0.1uF ceramic capacitor placed within 5 mm of each supply pin. The Analog Devices evaluation board uses separate AVDD/DVDD planes; if using a single 1.8V plane, place a ferrite bead between the analog and digital supply pins to isolate switching noise from the analog front-end. Poor decoupling is the most common cause of SNR degradation below the 77 dB datasheet specification.
Route the analog inputs (AIN1+/- and AIN2+/-) as 100 ohm differential striplines or microstrips with controlled impedance, kept as short as possible and length-matched between the two channels to within 0.5 mm to preserve phase matching. The common-mode voltage (VCM) output pin should be decoupled with 0.1uF and used to set the input common-mode of upstream op-amps or transformers. Avoid routing digital outputs beneath the analog input traces to minimize digital-to-analog coupling.
Use a 4-layer or 6-layer PCB stack-up with dedicated ground and power planes. Place the LTC2191CUKG as close as possible to the analog front-end (driver amplifier) and the FPGA/ASIC receiver, keeping the analog and digital sections separated. The 7x8 mm 52-QFN package has 0.5 mm pitch; use NSMD pads with 0.3 mm via-in-pad for the exposed pad thermal vias. Reference: Analog Devices DC2192 evaluation kit layout.
Avoid using bipolar analog inputs exceeding 2 Vp-p differential - the absolute maximum differential input is 2.5 Vp-p per the Analog Devices datasheet, and overdrive will permanently damage the input ESD structures. Do not float the OFM pin; it must be tied high for LVDS or low for CMOS. Do not leave SENSE floating - it configures the internal reference (tie to AVDD for internal reference, or to GND for external reference). The LTC2180IUP is NOT a drop-in replacement (different 64-pin package, requires PCB redesign).
合规信息
LTC2191CUKG#PBF suffix indicates Pb-free (lead-free) finish and full RoHS compliance. Not AEC-Q100 qualified - the part is intended for commercial/industrial communications and instrumentation, not automotive. Halogen-free status not stated in the datasheet excerpt - see manufacturer product page for confirmation.
