LTC2267CUJ-12 - 12-Bit 105Msps Dual ADC, Low Power | ADI
料号： LTC2267CUJ-12 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $39.85 | $398.50 |
| 100 | $36.2 | $3,620.00 |
| 500 | $32.78 | $16,390.00 |
| 1,000 | $29.95 | $29,950.00 |
LTC2267CUJ-12 概述
A dual pipelined ADC is a member of the high-speed converter family in the data-converter hierarchy, which itself sits inside the broader mixed-signal IC category of power management and signal-conditioning devices. Within that hierarchy, a pipelined ADC is the de-facto choice for sample rates between roughly 1 Msps and 500 Msps because it offers an excellent trade-off between speed, resolution, and silicon area; the dual-channel variant extends this to multi-antenna, I/Q, or diversity receiver systems where two coherent conversions are needed from the same clock.
Key features of the LTC2267CUJ-12 include low 0.3 LSB RMS transition noise, serial LVDS outputs that minimize data-line count, internal bypassed reference, and a flexible clock duty-cycle stabilizer. The integrated 2-lane output mode reduces the FPGA pin count while still delivering both bits of each conversion in parallel; the 1-lane mode further reduces routing complexity at lower sample rates. A SPI-compatible serial interface allows per-channel gain, offset, and phase trim for channel matching.
The device is specified over the commercial 0 °C to +70 °C operating range with the LTC2267IUJ-12 industrial-grade variant covering -40 °C to +85 °C. The 40-pin QFN (6x6 mm) package exposes the die ground paddle on the bottom for low-impedance grounding and thermal relief, and is pin-compatible with the broader LTC226x-12/14 family of 12-/14-bit dual ADCs from Analog Devices.
Typical applications include multi-antenna wireless receivers, software-defined radio (SDR) front-ends, I/Q baseband digitization, low-power portable instrumentation, medical imaging receive channels, and LTE/3G diversity radio paths. Designers often pair the LTC2267CUJ-12 with an LT6203 or ADA4937 driver in front and an FPGA such as a Xilinx Spartan-6 or Altera Cyclone IV on the LVDS side.
A key design consideration is LVDS trace length matching: the two bits of each conversion must be deskewed by the receiver, so pairs should be routed with controlled impedance (100 Ω differential) and matched to within roughly 100 mil. The exposed pad must be soldered to a continuous ground plane for both electrical and thermal reasons; bypassing the 1.8 V analog supply with 10 µF bulk plus 0.1 µF ceramic at every pin is essential to meet the noise floor at 105 Msps.
This page synthesizes distributor stock, drop-in compatible pin-compatible LTC226x family members, and practical LVDS-layout design guidance not found in the manufacturer datasheet.
直接替换替代料： LTC2267CUJ-12 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2267CUJ-12 （相同外形与封装尺寸） ——差异在于 Operating Temperature, Resolution, Package, Analog Supply Voltage, Input Type.
快速对比工具——选择替代料号进行并排对比：
LTC2267IUJ-12
✅ 直接替换📋 参考替代料（不在目录中）
LTC2267CUJ-14
✅ 直接替换✓ 有现货
$40.99 / 个
查看数据手册 →LTC2266CUJ-12
✅ 直接替换✓ 有现货
$11.5 / 个
查看数据手册 →LTC2265CUJ-12
✅ 直接替换✓ 有现货
$22.4 / 个
查看数据手册 →LTC2263CUJ-12
✅ 直接替换✓ 有现货
$19.2 / 个
查看数据手册 →LTC2267CUJ-12 最大额定值与电气特性
| 分辨率 | 12 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 105 Msps |
| Architecture | Pipelined |
| Analog Supply Voltage | 1.8 V (typ) |
| INL (typical) | ±0.3 LSB |
| DNL (typical) | ±0.1 LSB |
| Transition Noise | 0.3 LSB RMS |
| Missing Codes | None (over temperature) |
| Digital Output | Serial LVDS, 1-lane or 2-lane mode |
| Input Type | Differential (per channel) |
| 封装 | 40-QFN (6x6 mm) with exposed pad |
| 工作温度 | 0 °C to +70 °C (commercial, CUJ suffix) |
| Reference | Internal (bypassed) |
| RoHS 状态 | Compliant (#PBF suffix) |
LTC2267CUJ-12 引脚配置
| 引脚 1 | INA+ — Channel A positive differential analog input |
| 引脚 2 | INA- — Channel A negative differential analog input |
| 引脚 3 | VCM_A — Channel A common-mode voltage bypass |
| 引脚 4 | REFT_A — Channel A reference decoupling |
| 引脚 5 | REFB_A — Channel A reference decoupling |
| 引脚 6 | VA — 1.8 V analog supply for channel A |
| 引脚 7 | GND — Analog ground |
| 引脚 8 | CLK_A — Channel A sample clock input (differential) |
| 引脚 9 | CLK_A- — Channel A sample clock complement |
| 引脚 10 | OF_A — Channel A overflow indicator (LVDS) |
| 引脚 11 | DA0_A+ — Channel A LVDS data bit 0 positive |
| 引脚 12 | DA0_A- — Channel A LVDS data bit 0 negative |
| 引脚 13 | DA1_A+ — Channel A LVDS data bit 1 positive (2-lane mode) |
| 引脚 14 | DA1_A- — Channel A LVDS data bit 1 negative (2-lane mode) |
| 引脚 15 | FCLK+ — Frame clock LVDS positive |
| 引脚 16 | FCLK- — Frame clock LVDS negative |
| 引脚 17 | DCO+ — Data clock LVDS positive |
| 引脚 18 | DCO- — Data clock LVDS negative |
| 引脚 19 | VD — 1.8 V digital supply (LVDS) |
| 引脚 20 | GND — Digital ground |
| 引脚 21 | INB+ — Channel B positive differential analog input |
| 引脚 22 | INB- — Channel B negative differential analog input |
| 引脚 23 | VCM_B — Channel B common-mode voltage bypass |
| 引脚 24 | REFT_B — Channel B reference decoupling |
| 引脚 25 | REFB_B — Channel B reference decoupling |
| 引脚 26 | VB — 1.8 V analog supply for channel B |
| 引脚 27 | GND — Analog ground |
| 引脚 28 | CLK_B — Channel B sample clock input (differential) |
| 引脚 29 | CLK_B- — Channel B sample clock complement |
| 引脚 30 | OF_B — Channel B overflow indicator (LVDS) |
| 引脚 31 | DB0_B+ — Channel B LVDS data bit 0 positive |
| 引脚 32 | DB0_B- — Channel B LVDS data bit 0 negative |
| 引脚 33 | DB1_B+ — Channel B LVDS data bit 1 positive (2-lane mode) |
| 引脚 34 | DB1_B- — Channel B LVDS data bit 1 negative (2-lane mode) |
| 引脚 35 | CS — Chip select / SPI serial interface |
| 引脚 36 | SCK — SPI serial clock |
| 引脚 37 | SDI — SPI serial data input |
| 引脚 38 | SDO — SPI serial data output |
| 引脚 39 | MODE — Output mode select (1-lane / 2-lane LVDS) |
| 引脚 40 | GND — Analog ground / exposed pad |
典型应用
LTC2267CUJ-12 适用于 6 应用s: Multi-Antenna Wireless Receiver (Diversity / MIMO), Software Defined Radio (SDR) Baseband Digitization, Low-Power Portable Instrumentation, Medical Imaging Receive Channel, Communications Test & Measurement, Industrial Process Control / Data Acquisition.
Multi-Antenna Wireless Receiver (Diversity / MIMO)
The LTC2267CUJ-12 is well-suited to multi-antenna wireless receivers where two coherent baseband or IF channels must be digitized simultaneously. Its 12-bit resolution at 105 Msps provides more than 70 dB SNR per channel, sufficient for 3G/4G diversity and 2x2 MIMO front-ends. The dual pipelined core guarantees matched gain and phase between channels, while the serial LVDS interface cuts FPGA pin count by roughly 4x versus parallel CMOS. Recommended placement: behind an LT6203 driver from each antenna chain, with a shared 105 MHz clock from a low-jitter PLL. Trade-off vs the LTC2267-14: 12 bits limits spurious-free dynamic range to about 78 dBFS, but saves ~30% cost.
推荐
Software Defined Radio (SDR) Baseband Digitization
Software-defined radio platforms benefit from the LTC2267CUJ-12's dual-channel sampling at 105 Msps, which captures both I and Q baseband signals from a single direct-conversion tuner in one synchronized snapshot. The 12-bit dynamic range comfortably handles DVB-T, LTE, and Wi-Fi spectrum masks after the front-end LNA and quadrature demodulator. The exposed-pad QFN keeps the PCB footprint small enough for portable SDR dongles, and the serial LVDS 1-lane mode cuts wiring complexity in tight enclosures. Pair with an ADA4937 differential driver and a Xilinx Spartan-6 FPGA for the digital down-conversion chain.
推荐
Low-Power Portable Instrumentation
Battery-powered oscilloscopes, spectrum analyzers, and handheld data-acquisition modules use the LTC2267CUJ-12 to digitize two channels simultaneously while staying within a tight power budget. At 1.8 V supply and 105 Msps, the part draws less than 200 mW per channel — small enough that a USB-powered enclosure can host the ADC, an LCD, and a small FPGA without active cooling. The internal reference and bypassed decoupling simplify the analog front-end to a single LTC2267 + driver + FPGA BOM. The 12-bit resolution is sufficient for general-purpose measurement where ENOB rather than raw SNR is the user-visible metric.
推荐
Medical Imaging Receive Channel
Ultrasound and optical-coherence-tomography (OCT) imaging systems leverage the LTC2267CUJ-12's dual pipelined channels to capture RF or interferometric data at 105 Msps with matched channel response. The 12-bit resolution is well-matched to mid-range ultrasound front-ends where penetration depth dominates over fine grayscale resolution. The internal reference eliminates external reference drift over the patient exam, while the exposed-pad QFN delivers uniform thermal behavior across both channels — important for color-Doppler stability. Compliance note: medical designs should select the LTC2267IUJ-12 industrial-temp variant for the wider operating range required by clinical environments.
推荐
Communications Test & Measurement
Bench-top signal analyzers and protocol testers digitize two-phase related waveforms simultaneously using the LTC2267CUJ-12. The 12-bit, 105 Msps capability captures multi-MHz modulated signals (WLAN, Bluetooth, Zigbee) with sufficient dynamic range for EVM measurement below 3%. Designers choose this part over 14-bit siblings when the measurement focus is modulation bandwidth rather than absolute amplitude accuracy, because the 12-bit version costs less and dissipates less heat in a sealed bench instrument. The serial LVDS output feeds directly into an FPGA-based vector signal analyzer for post-processing.
推荐
Industrial Process Control / Data Acquisition
Multi-channel industrial DAQ modules use the LTC2267CUJ-12 as the per-pair sampler behind a multiplexer and instrumentation amplifier. The simultaneous-sampling dual channels let a single ADC handle two sensors — for example a strain gauge and a thermocouple amplifier — with deterministic phase relationship. The 12-bit resolution aligns with the 0.1% accuracy class common in PLC analog input modules, while the 105 Msps headroom means designers can oversample and decimate for noise reduction. The 0 °C to +70 °C commercial range covers most factory-floor environments; for outdoor or -40 °C cabinets, the LTC2267IUJ-12 variant is recommended.
推荐
推荐产品汇总
工程参考数据： LTC2267CUJ-12 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2267IUJ-12 | LTC2267CUJ-14 | LTC2266CUJ-12 | LTC2265CUJ-12 | LTC2263CUJ-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 12 bit | 12 bit (same) | 14 bit (+2 bits) | 12 bit (same) | 12 bit (same) | 12 bit (same) |
| Sample Rate | 105 Msps | 105 Msps (same) | 105 Msps (same) | 80 Msps (-24%) | 65 Msps (-38%) | 25 Msps (-76%) |
| Number of Channels | 2 (dual) | 2 (same) | 2 (same) | 2 (same) | 2 (same) | 2 (same) |
| Output Interface | Serial LVDS | Serial LVDS (same) | Serial LVDS (same) | Serial LVDS (same) | Serial LVDS (same) | Serial LVDS (same) |
| Operating Temperature | 0 to +70 C | -40 to +85 C (wider) | 0 to +70 C (same) | 0 to +70 C (same) | 0 to +70 C (same) | 0 to +70 C (same) |
| INL (typical) | ±0.3 LSB | ±0.3 LSB (same) | ±0.5 LSB (typ) | ±0.3 LSB (same) | ±0.3 LSB (same) | ±0.3 LSB (same) |
关键差异点
- Wider operating temperature in identical footprint via the IUJ-12 variant （对比 LTC2267IUJ-12)
- Two extra bits of resolution on the same 40-QFN footprint （对比 LTC2267CUJ-14)
- 25% lower sample rate and ~15% lower power at the same footprint （对比 LTC2266CUJ-12)
设计说明
The 40-QFN (6x6) exposed pad MUST be soldered to a continuous ground plane with at least 9 thermal vias arranged in a 3x3 array beneath the pad. Skipping this step degrades INL by 1-2 LSB and increases reference noise coupling, because the pad is the primary return path for both analog currents and thermal relief. Use 0.20 mm via drill with 0.40 mm pitch to maximize solder wicking without violating clearance.
Route each LVDS pair (DA0/DA1/DCO/FCLK and their complements) over a continuous reference plane with 100 Ω differential impedance and matched length to within 100 mil. Place a 100 Ω termination resistor between each pair at the receiver FPGA within 5 mm of the FPGA pin. If using 2-lane LVDS mode, match the DCO pair to the data pairs to within 50 mil for proper bit alignment at the FPGA IDDR register.
Bypass the 1.8 V analog supply (VA, VB) with a 10 µF X7R bulk plus 0.1 µF ceramic capacitor placed within 2 mm of each supply pin. Ferrite beads separating VA/VB from VD (digital 1.8 V) prevent digital switching noise from coupling into the analog reference. Place the ferrite between the regulator output and the analog pin, not the other way around, to maximize high-frequency isolation.
Do not float the MODE pin — leaving it open selects an undefined output mode. Tie MODE high for 2-lane LVDS, low for 1-lane LVDS per the LTC2267 family datasheet. Likewise, do not assume CLK_A and CLK_B can be driven from a single-ended source; the part expects a differential clock and a single-ended clock increases aperture jitter by ~30 ps RMS.
合规信息
RoHS and lead-free compliance confirmed by the #PBF ordering suffix per Analog Devices product marking conventions. Halogen-free status not explicitly stated in the verified web data and listed as unknown.