LTC2285CUP - Dual 14-Bit 125Msps Low-Power 3V ADC | ADI
料号： LTC2285CUP ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $119.55 | $119.55 |
| 10 | $105.2 | $1,052.00 |
| 100 | $89.4 | $8,940.00 |
| 500 | $78.9 | $39,450.00 |
| 1,000 | $71.85 | $71,850.00 |
| 2,500 | $65.1 | $162,750.00 |
LTC2285CUP 概述
A pipelined ADC is a multi-stage conversion architecture that uses a cascade of low-resolution flash stages and digital correction logic to achieve high sampling rates with moderate-to-high resolution, while consuming far less power than a full-flash converter of equivalent resolution. The LTC2285CUP sits in the product hierarchy of: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor, and is a member of ADI's broad family of low-power, high-performance 3V ADCs.
Key features of the LTC2285CUP include dual 14-bit 125 MSPS conversion, integrated input PGA, single 3V supply operation, low power dissipation near 235 mW total at full speed, and pin-selectable input ranges. Differential inputs with on-chip track-and-hold circuits minimize aperture jitter, and an internal duty-cycle stabilizer compensates for variations in the clock duty cycle to preserve SNR at high input frequencies.
Typical applications include cellular base-station receiver IF digitizers, ultrasound imaging front ends, cable head-end digital receivers, and high-speed digital oscilloscopes. When using the LTC2285CUP, careful attention should be paid to analog input common-mode voltage and clock jitter: the SNR degrades with finite clock aperture jitter, so designers should use a low-jitter clock source and follow ADI's standard 50-ohm matched differential input network to preserve AC performance. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not consolidated in the manufacturer datasheet, helping engineers shorten part selection and BOM qualification cycles.
直接替换替代料： LTC2285CUP ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2285CUP （相同外形与封装尺寸） ——差异在于 RoHS Status, Package, SFDR, Number of Channels, Resolution.
快速对比工具——选择替代料号进行并排对比：
LTC2285IUP
✅ 直接替换📋 参考替代料（不在目录中）
LTC2282CUP
✅ 直接替换✓ 有现货
$18.5 / 个
查看数据手册 →LTC2280CUP
✅ 直接替换✓ 有现货
$15.85 / 个
查看数据手册 →LTC2283CUP
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$38.95 / 个
查看数据手册 →LTC2241IUP-12
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$34.5 / 个
查看数据手册 →LTC2285CUP 最大额定值与电气特性
| Manufacturer | Analog Devices Inc. |
| 分辨率 | 14 bit |
| Number of Channels | 2 (Dual) |
| 采样率 | 125 MSPS |
| Architecture | Pipelined |
| Input Type | Differential / Single-Ended |
| 电源电压 | 2.85 V to 3.4 V (3 V nominal) |
| Power Dissipation | 235 mW typical (dual, full rate) |
| SNR | 72.2 dB at Nyquist input |
| SFDR | 82 dB at Nyquist input |
| Input Range | 1 Vp-p-p pk to 2 Vp-p differential, pin selectable |
| Integral Nonlinearity (INL) | ±1 LSB typical |
| Package Type | 64-QFN (9x9 mm) - HVQCCN |
| 工作温度 | 0C to +70C (Commercial grade) |
| RoHS 状态 | Compliant |
| Lead-Free / PBF | Yes (#PBF suffix variants) |
| 安装类型 | Surface Mount |
LTC2285CUP 引脚配置
| 引脚 1 | AIN1+ — Channel 1 differential analog input positive |
| 引脚 2 | AIN1- — Channel 1 differential analog input negative |
| 引脚 3 | VCM1 — Common-mode voltage reference, channel 1 |
| 引脚 4 | SENSE — Input range select |
| 引脚 5 | GND — Analog ground |
| 引脚 6 | VDD — Analog 3V supply |
| 引脚 7 | VREF — Voltage reference bypass |
| 引脚 8 | OGND — Output driver ground |
| 引脚 9 | OVDD — Output driver supply |
| 引脚 10 | CLK+ — Clock input positive |
| 引脚 11 | CLK- — Clock input negative |
| 引脚 12 | D0_1 — Channel 1 data output bit 0 (LSB) |
| 引脚 13 | D1_1 — Channel 1 data output bit 1 |
| 引脚 14 | D2_1 — Channel 1 data output bit 2 |
| 引脚 15 | D3_1 — Channel 1 data output bit 3 |
| 引脚 16 | D4_1 — Channel 1 data output bit 4 |
| 引脚 17 | D5_1 — Channel 1 data output bit 5 |
| 引脚 18 | D6_1 — Channel 1 data output bit 6 |
| 引脚 19 | D7_1 — Channel 1 data output bit 7 |
| 引脚 20 | D8_1 — Channel 1 data output bit 8 |
| 引脚 21 | D9_1 — Channel 1 data output bit 9 |
| 引脚 22 | D10_1 — Channel 1 data output bit 10 |
| 引脚 23 | D11_1 — Channel 1 data output bit 11 |
| 引脚 24 | D12_1 — Channel 1 data output bit 12 |
| 引脚 25 | D13_1 — Channel 1 data output bit 13 (MSB) |
| 引脚 26 | OF_1 — Channel 1 overflow flag |
| 引脚 27 | ENC1+ — Channel 1 encode clock positive (output) |
| 引脚 28 | ENC1- — Channel 1 encode clock negative (output) |
| 引脚 29 | OVDD — Output driver supply |
| 引脚 30 | OGND — Output driver ground |
| 引脚 31 | OF_2 — Channel 2 overflow flag |
| 引脚 32 | D13_2 — Channel 2 data output bit 13 (MSB) |
| 引脚 33 | D12_2 — Channel 2 data output bit 12 |
| 引脚 34 | D11_2 — Channel 2 data output bit 11 |
| 引脚 35 | D10_2 — Channel 2 data output bit 10 |
| 引脚 36 | D9_2 — Channel 2 data output bit 9 |
| 引脚 37 | D8_2 — Channel 2 data output bit 8 |
| 引脚 38 | D7_2 — Channel 2 data output bit 7 |
| 引脚 39 | D6_2 — Channel 2 data output bit 6 |
| 引脚 40 | D5_2 — Channel 2 data output bit 5 |
| 引脚 41 | D4_2 — Channel 2 data output bit 4 |
| 引脚 42 | D3_2 — Channel 2 data output bit 3 |
| 引脚 43 | D2_2 — Channel 2 data output bit 2 |
| 引脚 44 | D1_2 — Channel 2 data output bit 1 |
| 引脚 45 | D0_2 — Channel 2 data output bit 0 (LSB) |
| 引脚 46 | OVDD — Output driver supply |
| 引脚 47 | OGND — Output driver ground |
| 引脚 48 | MODE — Output mode / test mode select |
| 引脚 49 | CS — Chip select (SPI control) |
| 引脚 50 | SCK — Serial clock (SPI control) |
| 引脚 51 | SDI — Serial data input (SPI control) |
| 引脚 52 | SDO — Serial data output (SPI control) |
| 引脚 53 | GAIN — Gain adjust / calibration |
| 引脚 54 | CAL — Calibration pin |
| 引脚 55 | MUX — Multiplexed channel select |
| 引脚 56 | VCM2 — Common-mode voltage reference, channel 2 |
| 引脚 57 | AIN2- — Channel 2 differential analog input negative |
| 引脚 58 | AIN2+ — Channel 2 differential analog input positive |
| 引脚 59 | GND — Analog ground |
| 引脚 60 | VDD — Analog 3V supply |
| 引脚 61 | VREF — Voltage reference bypass |
| 引脚 62 | ENC2- — Channel 2 encode clock negative (output) |
| 引脚 63 | ENC2+ — Channel 2 encode clock positive (output) |
| 引脚 64 | GND — Analog ground / exposed pad |
典型应用
LTC2285CUP 适用于 6 应用s: Cellular Base-Station Receiver IF Sampling, Ultrasound Imaging Front End, Cable Head-End Digital Receiver, High-Speed Digital Oscilloscope / Data Acquisition, Software Defined Radio (SDR) Wideband Digitizer, Industrial Non-Destructive Testing (NDT) Imaging.
Cellular Base-Station Receiver IF Sampling
The LTC2285CUP is well-suited for cellular base-station IF sampling because its dual 14-bit, 125 MSPS conversion and 72.2 dB SNR enable high dynamic range digitization of intermediate-frequency signals. The on-chip duty-cycle stabilizer preserves SNR with practical 30 to 50 percent duty clocks commonly generated in base-station ASICs, and the 64-QFN package supports standard 50-ohm matched differential input networks. AC performance is 82 dB SFDR at Nyquist, comfortably exceeding 3GPP spurious requirements for multi-carrier GSM/WCDMA receivers. Designers typically place the LTC2285CUP downstream of an IF SAW filter, with the analog inputs AC-coupled through a 1:1 transformer or differential driver such as the AD8138. Estimated power dissipation is approximately 235 mW at 125 MSPS, fitting standard fan-cooled line-card thermal envelopes.
推荐
Ultrasound Imaging Front End
In ultrasound imaging the LTC2285CUP provides two simultaneous 14-bit, 125 MSPS channels for beamformed RF signal digitizing, with low 235 mW power enabling dense channel arrays. The 72.2 dB SNR and 82 dB SFDR support the wide dynamic range required to resolve small return echoes alongside strong reflectors, while the pin-selectable 1 or 2 Vp-p differential input range lets designers optimize full-scale headroom across transducer channels. Typical ultrasound front ends place the LTC2285CUP immediately after the LNA and time-gain compensation stage, AC-coupled with 50-ohm transformer networks. Low aperture jitter preserves phase coherence across receive channels, critical for phased-array beamforming accuracy. The 64-QFN (9x9 mm) footprint also suits compact probe-head electronics.
推荐
Cable Head-End Digital Receiver
Cable head-end digital receivers digitize densely packed QAM carriers, demanding high spurious-free dynamic range from the ADC. The LTC2285CUP delivers 82 dB SFDR and 72.2 dB SNR at Nyquist, comfortably resolving hundreds of QAM channels aggregated onto a single ADC input. The dual-channel capability lets one LTC2285CUP digitize both I and Q paths of a complex demodulated IF, or two independent downstream bands. Per the Analog Devices datasheet, the part supports single 3V supply operation, simplifying head-end power tree design. Designers typically use a broadband balun network feeding the differential inputs, followed by a digital down-converter in the FPGA. The 64-QFN exposed pad aids thermal dissipation at continuous 125 MSPS dual-channel operation.
推荐
High-Speed Digital Oscilloscope / Data Acquisition
The LTC2285CUP serves well in high-speed oscilloscope and data acquisition front ends where 14-bit resolution at 125 MSPS per channel strikes a balance between bandwidth and DC accuracy. Two simultaneous sampling channels support 2-channel scope architectures or time-interleaved higher-speed systems. The differential inputs reject common-mode noise in mixed analog/digital environments, while the on-chip track-and-hold minimizes aperture jitter for accurate transient capture. The 64-QFN (9x9 mm) package enables compact front-end PCBs, and the 235 mW typical dissipation eases thermal management in densely-populated instrument chassis. Designers typically clock the LTC2285CUP from a low-jitter TCXO and pair it with a high-bandwidth front-end attenuator and amplifier network.
推荐
Software Defined Radio (SDR) Wideband Digitizer
Software defined radio platforms benefit from the LTC2285CUP's dual 14-bit 125 MSPS capability when digitizing IF or RF signals directly for FPGA-based digital down-conversion. With 72.2 dB SNR and 82 dB SFDR the ADC captures both strong and weak signals in contested RF environments, supporting multi-mode SDR receiver designs. The single 3V supply simplifies portable and rugged SDR power trees, and the 64-QFN exposed pad aids thermal dissipation in sealed enclosures. AC coupling through a wideband transformer network is standard, and designers often pair the LTC2285CUP with an FPGA such as the Xilinx Spartan-6 for real-time demodulation. The pin-selectable 1 or 2 Vp-p input range allows flexible matching to front-end LNA outputs.
推荐
Industrial Non-Destructive Testing (NDT) Imaging
Industrial non-destructive testing systems, including ultrasonic flaw detectors and eddy-current arrays, leverage the LTC2285CUP's dual 14-bit 125 MSPS sampling to digitize high-bandwidth transducer return signals. The 72.2 dB SNR cleanly resolves small flaws in metallic structures, while the 82 dB SFDR suppresses harmonic distortion that could mimic defect signatures. Commercial 0C to +70C operation matches indoor NDT laboratory environments; for harsh-field deployments the pin-compatible LTC2285IUP is a drop-in upgrade. The 64-QFN footprint supports compact portable probe electronics, and single 3V operation simplifies battery-powered NDT instruments. Designers typically clock the LTC2285CUP from a stable TCXO and synchronize acquisition to a pulser-echo cycle.
推荐
推荐产品汇总
工程参考数据： LTC2285CUP ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2285IUP | LTC2282CUP | LTC2280CUP | LTC2283CUP | LTC2241IUP-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit |
| Sampling Rate | 125 MSPS | 125 MSPS | 105 MSPS | 80 MSPS | 80 MSPS | 40 MSPS |
| Number of Channels | 2 (Dual) | 2 (Dual) | 2 (Dual) | 2 (Dual) | 2 (Dual) | 2 (Dual) |
| Operating Temperature | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
| Supply Voltage | 3V (2.85 V to 3.4 V) | 3V (2.85 V to 3.4 V) | 3V (2.85 V to 3.4 V) | 3V (2.85 V to 3.4 V) | 3V (2.85 V to 3.4 V) | 3V (2.85 V to 3.4 V) |
关键差异点
- Dual 14-bit 125 MSPS with 72.2 dB SNR at Nyquist （对比 LTC2280CUP (80 MSPS))
- Industrial-grade drop-in option without PCB rework （对比 LTC2285IUP)
- 14-bit resolution advantage over 12-bit family members （对比 LTC2241IUP-12)
设计说明
Place the LTC2285CUP analog input traces symmetrically and use 50-ohm controlled-impedance routing from the transformer secondary to the AIN1+/AIN1- and AIN2+/AIN2- pins. Length matching within 0.5 mm preserves the differential balance that maintains 72.2 dB SNR. Per the Analog Devices datasheet, the exposed thermal pad (pin 64) must be soldered to a continuous ground plane with multiple vias stitching the top and bottom layers for low-impedance return current.
Decouple each VDD pin with a 0.1 uF X7R ceramic capacitor placed within 2 mm of the pin, plus a 10 uF tantalum bulk capacitor on each supply plane. Use a ferrite bead to isolate analog VDD from digital OVDD to prevent digital switching noise from coupling into the analog front end. Estimated: with 235 mW typical dissipation at 125 MSPS dual-channel operation, the 64-QFN exposed pad keeps junction rise under 35C above ambient on a standard 4-layer 1 oz PCB.
Drive the CLK+/CLK- differential clock with a low-jitter source (typically less than 1 ps RMS). The LTC2285CUP SNR degrades proportionally to aperture jitter, so avoid using a 3V CMOS single-ended clock directly. Per the Analog Devices datasheet, an AC-coupled LVPECL or sinusoidal clock preserves the 72.2 dB SNR at Nyquist. The internal duty-cycle stabilizer compensates for 30 to 70 percent clock duty cycles but does not correct jitter.
Avoid routing the digital output bus (D0_1..D13_1, D0_2..D13_2, OF_1, OF_2) parallel to or beneath the analog input traces. Even on a 4-layer PCB, digital edge coupling can degrade SNR by 5 to 10 dB. Per the Analog Devices datasheet, place a ground pour between the analog and digital sections and route output traces on the opposite side of the PCB with matched 50-ohm impedance to the FPGA receiver bank.
合规信息
RoHS and lead-free per Analog Devices product page. #PBF suffix indicates Pb-free compliance. Not AEC-Q100 qualified - choose industrial-grade variant for harsh environments.
