LTC2286CUP - Dual 10-Bit 25Msps Low-Noise 3V ADC | Analog Devices
料号： LTC2286CUP ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.85 | $128.50 |
| 100 | $11.2 | $1,120.00 |
| 500 | $10.05 | $5,025.00 |
| 1,000 | $9.56 | $9,560.00 |
LTC2286CUP 概述
An analog-to-digital converter (ADC) is a semiconductor device that transforms continuous analog signals into discrete digital codes for processing by digital systems. Pipeline ADCs like the LTC2286 use a multistage architecture to achieve high sampling rates while keeping power and die area low, sitting between successive-approximation register (SAR) ADCs (lower speed, lower power) and flash ADCs (highest speed, highest power) in the data-converter hierarchy. Dual-channel pipeline ADCs are especially important for communications, imaging, and I/Q demodulation where two correlated channels must be digitized simultaneously with matched gain, offset, and phase.
Key features include a 61.6 dB signal-to-noise ratio (SNR) and 85 dB spurious-free dynamic range (SFDR) at a 70 MHz analog input, 110 dB crosstalk isolation at 100 MHz, and flexible input ranges up to 2 V peak-to-peak. The part supports multiplexed or simultaneous sampling of the two channels, configurable via the MUX pin, and includes an internal voltage reference as well as an option for an external reference. The 64-pin exposed-pad QFN package provides a low thermal resistance path, allowing the 150 mW typical dissipation to be handled without an external heatsink.
The LTC2286 uses a proprietary multi-stage pipelined architecture with proprietary SHA front-end and on-chip sample-and-hold, internal bandgap reference, and programmable output data formatting (CMOS single-ended or LVDS). The flexible digital interface simplifies connection to FPGAs and DSPs, while the input common-mode circuitry allows DC- or AC-coupled inputs with single-ended or differential drive.
Typical applications include cellular base-station receivers, I/Q demodulation in software-defined radio (SDR), medical imaging front ends, CCD imaging digitizers, and low-cost digital oscilloscope input channels. The combination of dual channels, low noise, and 25 Msps speed makes it especially attractive for IF-sampling receivers in wireless infrastructure.
When designing with the LTC2286CUP, ensure the analog inputs are driven with low-impedance, bandwidth-appropriate amplifiers and that the exposed pad is soldered to a sufficient copper pour for thermal dissipation. Decoupling the 3V analog and digital supplies close to the pins is critical to achieving the rated SNR/SFDR performance.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement the Analog Devices datasheet, giving engineers a single reference for sourcing and selection decisions.
直接替换替代料： LTC2286CUP ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2286CUP （相同外形与封装尺寸） ——差异在于 Package, RoHS Status, Input Type, Operating Temperature Range, Sample Rate.
快速对比工具——选择替代料号进行并排对比：
LTC2287CUP
✅ 直接替换✓ 有现货
$7.05 / 个
查看数据手册 →LTC2288CUP
✅ 直接替换✓ 有现货
$9.05 / 个
查看数据手册 →LTC2286IUP
✅ 直接替换📋 参考替代料（不在目录中）
LTC2286CUP#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2282CUP
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$18.5 / 个
查看数据手册 →LTC2286CUP 最大额定值与电气特性
| 分辨率 | 10 bits |
| Number of Channels | 2 (dual) |
| Sample Rate | 25 Msps |
| Architecture | Pipelined |
| 电源电压 | 3 V (single, up to 3.4 V) |
| Power Consumption | 150 mW typical at 25 Msps |
| SNR | 61.6 dB at 70 MHz input |
| SFDR | 85 dB at 70 MHz input |
| Channel Isolation / Crosstalk | 110 dB at 100 MHz |
| Input Range | Up to 2 V peak-to-peak |
| Data Output Interface | CMOS or LVDS, configurable |
| 封装 | 64-pin QFN (9x9 mm, HVQCCN) with exposed pad |
| 工作温度范围 | 0 C to +70 C (commercial, 'C' grade) |
| Operating Mode | Multiplexed or simultaneous sampling |
| Reference | Internal, with external reference option |
| RoHS 状态 | Compliant (lead-free #PBF suffix) |
| 1ku List Price (starting) | $9.56 (as of 2026-10-13) |
LTC2286CUP 引脚配置
| 引脚 1 | OGND — Output driver ground |
| 引脚 2 | OVDD — Output driver supply |
| 引脚 3 | D9A — Channel A data output bit 9 (MSB) |
| 引脚 4 | D8A — Channel A data output bit 8 |
| 引脚 5 | D7A — Channel A data output bit 7 |
| 引脚 6 | D6A — Channel A data output bit 6 |
| 引脚 7 | D5A — Channel A data output bit 5 |
| 引脚 8 | D4A — Channel A data output bit 4 |
| 引脚 9 | OGND — Output driver ground |
| 引脚 10 | OVDD — Output driver supply |
| 引脚 11 | D3A — Channel A data output bit 3 |
| 引脚 12 | D2A — Channel A data output bit 2 |
| 引脚 13 | D1A — Channel A data output bit 1 |
| 引脚 14 | D0A — Channel A data output bit 0 (LSB) |
| 引脚 15 | OFCH_A — Channel A output format / clock |
| 引脚 16 | CLKOUTA — Channel A clock output |
| 引脚 17 | OGND — Output driver ground |
| 引脚 18 | OVDD — Output driver supply |
| 引脚 19 | OGND — Output driver ground |
| 引脚 20 | OVDD — Output driver supply |
| 引脚 21 | D9B — Channel B data output bit 9 (MSB) |
| 引脚 22 | D8B — Channel B data output bit 8 |
| 引脚 23 | D7B — Channel B data output bit 7 |
| 引脚 24 | D6B — Channel B data output bit 6 |
| 引脚 25 | D5B — Channel B data output bit 5 |
| 引脚 26 | D4B — Channel B data output bit 4 |
| 引脚 27 | OGND — Output driver ground |
| 引脚 28 | OVDD — Output driver supply |
| 引脚 29 | D3B — Channel B data output bit 3 |
| 引脚 30 | D2B — Channel B data output bit 2 |
| 引脚 31 | D1B — Channel B data output bit 1 |
| 引脚 32 | D0B — Channel B data output bit 0 (LSB) |
| 引脚 33 | OFCH_B — Channel B output format / clock |
| 引脚 34 | CLKOUTB — Channel B clock output |
| 引脚 35 | OGND — Output driver ground |
| 引脚 36 | OVDD — Output driver supply |
| 引脚 37 | DGND — Digital ground |
| 引脚 38 | DVDD — Digital supply |
| 引脚 39 | MODE — Output mode select (CMOS/LVDS) |
| 引脚 40 | MUX — Multiplexed/simultaneous sampling select |
| 引脚 41 | SHDN — Shutdown (active low) |
| 引脚 42 | SENSE — Reference mode select |
| 引脚 43 | VREF — Reference voltage (bypass/decoupling) |
| 引脚 44 | REFCOMP — Reference compensation pin |
| 引脚 45 | AGND — Analog ground |
| 引脚 46 | AVDD — Analog supply |
| 引脚 47 | INA+ — Channel A positive analog input |
| 引脚 48 | INA- — Channel A negative analog input |
| 引脚 49 | AGND — Analog ground |
| 引脚 50 | AVDD — Analog supply |
| 引脚 51 | INB+ — Channel B positive analog input |
| 引脚 52 | INB- — Channel B negative analog input |
| 引脚 53 | AGND — Analog ground |
| 引脚 54 | AVDD — Analog supply |
| 引脚 55 | CLKB- — Channel B clock negative input |
| 引脚 56 | CLKB+ — Channel B clock positive input |
| 引脚 57 | AGND — Analog ground |
| 引脚 58 | AVDD — Analog supply |
| 引脚 59 | CLKA- — Channel A clock negative input |
| 引脚 60 | CLKA+ — Channel A clock positive input |
| 引脚 61 | AGND — Analog ground |
| 引脚 62 | AVDD — Analog supply |
| 引脚 63 | ENC — Encode clock input |
| 引脚 64 | ENC- — Encode clock negative input |
典型应用
LTC2286CUP 适用于 7 应用s: Cellular Base-Station IF Sampling, I/Q Demodulation in Software-Defined Radio (SDR), Medical Imaging Front End, CCD Imaging Digitizer, Low-Cost Digital Oscilloscope Input Channel, Industrial Vibration and Acoustic Analysis, Portable Test and Measurement Instrumentation.
Cellular Base-Station IF Sampling
The LTC2286CUP is well suited for cellular base-station IF-sampling receivers because of its 61.6 dB SNR at 70 MHz and 85 dB SFDR at 70 MHz, which provide the dynamic range required for wideband IF digitization. The dual-channel architecture supports direct I/Q sampling from a single ADC, eliminating the need for two separate converters. Operating from a single 3V supply at only 150 mW keeps board-level power dissipation low; this is critical for densely populated base-station line cards where multiple receive paths must coexist on one PCB. Pair it with the AD8138 differential driver on the input and an FPGA on the LVDS output side for a complete receiver chain.
推荐
I/Q Demodulation in Software-Defined Radio (SDR)
The dual-channel, simultaneous-sampling capability of the LTC2286CUP makes it an excellent fit for I/Q demodulation in software-defined radio platforms where I and Q baseband channels must be digitized with matched gain, offset, and phase. The 110 dB channel-to-channel isolation at 100 MHz ensures that crosstalk between the I and Q paths does not corrupt the demodulated signal constellation, which is essential for high-order QAM and OFDM waveforms. At 25 Msps per channel the converter comfortably digitizes baseband bandwidths up to 12.5 MHz, covering many narrowband and wideband SDR receiver applications from HF through L-band.
推荐
Medical Imaging Front End
The LTC2286CUP serves well in medical imaging front ends such as ultrasound receivers, where its 25 Msps sample rate, 61.6 dB SNR, and dual-channel architecture support simultaneous digitization of multiple transducer channels. Ultrasound systems typically require 8-12 bits of effective resolution at 20-40 Msps, and the LTC2286CUP meets those requirements while consuming only 150 mW per converter, enabling compact, low-heat-density designs that are easier to keep within thermal-envelope limits. The 64-pin QFN package also helps minimize PCB area, which is critical in portable or cart-based ultrasound systems.
推荐
CCD Imaging Digitizer
The LTC2286CUP is an excellent match for digitizing the analog outputs of CCD image sensors in industrial inspection cameras, broadcast cameras, and scientific imaging systems. CCD output signals typically swing 0.5-1 V with high-frequency content up to several MHz; the 25 Msps sample rate and 2 V peak-to-peak input range of the LTC2286CUP accommodate a wide variety of pixel clock rates without aliasing. The dual-channel architecture allows simultaneous capture of odd/even pixel pairs, simplifying downstream demosaicing. Low 150 mW dissipation helps the camera head stay cool, reducing dark-current drift in the CCD itself.
推荐
Low-Cost Digital Oscilloscope Input Channel
The LTC2286CUP can be used in low-cost digital oscilloscope input channels where 25 Msps is sufficient (e.g. audio-bandwidth or low-frequency measurement instruments). Its 61.6 dB SNR yields roughly 10 effective bits at the Nyquist limit, and the 85 dB SFDR ensures that large input tones do not produce spurious harmonics that would mislead users. The dual-channel architecture enables two channels of acquisition per converter, halving board area and BOM cost in 2-channel oscilloscope designs. The LVDS-compatible digital output simplifies connection to an FPGA or DSP that performs triggering, timebase, and display rendering.
推荐
Industrial Vibration and Acoustic Analysis
The LTC2286CUP supports industrial vibration monitoring and acoustic analysis systems where dual-channel simultaneous sampling is needed to capture correlated signals such as accelerometer outputs or microphone pairs. The 25 Msps per channel rate easily captures vibration spectra above 100 kHz and acoustic spectra into the ultrasonic range, while the 61.6 dB SNR preserves measurement accuracy at low signal levels. The 3V single-supply operation simplifies power-supply design in battery-powered field instrumentation, and the 64-pin QFN package provides a compact footprint for portable analyzer designs.
推荐
Portable Test and Measurement Instrumentation
The LTC2286CUP is well suited to portable test-and-measurement instruments like handheld spectrum analyzers, RF signal analyzers, and data-acquisition modules, where low power, small size, and dual-channel capability are all essential. At 150 mW from a 3V supply and a 9x9 mm QFN footprint, the part enables battery-powered designs that run for hours on a single charge. The dual-channel architecture supports simultaneous capture of two input signals (e.g. stimulus and response in a Bode-plot measurement), while the LVDS output interface minimizes digital noise coupling into the analog front end.
推荐
推荐产品汇总
工程参考数据： LTC2286CUP ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2287CUP | LTC2288CUP | LTC2286IUP | LTC2286CUP#PBF | LTC2282CUP |
|---|---|---|---|---|---|---|
| Package | 64-pin QFN (9x9 mm, HVQCCN) | 64-pin QFN (9x9 mm, HVQCCN) - same | 64-pin QFN (9x9 mm, HVQCCN) - same | 64-pin QFN (9x9 mm, HVQCCN) - same | 64-pin QFN (9x9 mm, HVQCCN) - same | 64-pin QFN (9x9 mm, HVQCCN) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits | 12 bits |
| Supply Voltage | 3 V (up to 3.4 V) | 3 V (up to 3.4 V) | 3 V (up to 3.4 V) | 3 V (up to 3.4 V) | 3 V (up to 3.4 V) | 3 V (up to 3.4 V) |
| Temperature Grade | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
关键差异点
- Lowest-power grade in the LTC2288/87/86 family （对比 LTC2287CUP)
- Lower power for 25 Msps performance （对比 LTC2288CUP)
- Commercial grade optimized for cost-sensitive designs （对比 LTC2286IUP)
- RoHS-compliant drop-in option （对比 LTC2286CUP (snPb))
设计说明
The LTC2286CUP requires the exposed pad of the 64-pin QFN to be soldered directly to a clean, unbroken ground pour on the top layer of the PCB, with multiple thermal vias stitching it to inner ground planes. According to the Analog Devices datasheet, the exposed pad is the primary thermal path for the 150 mW dissipation; failure to solder it properly can raise junction temperature by 20-30 C and degrade SNR/SFDR. Place at least 9 thermal vias (0.3 mm drill, 0.5 mm pitch) directly under the pad to provide a low-impedance thermal and electrical return.
Decouple AVDD, DVDD, and OVDD separately with 10 uF bulk capacitors placed within 5 mm of the pins and 0.1 uF X7R ceramics within 2 mm, per Analog Devices high-speed ADC layout guidance. Use a ferrite bead between the analog and digital 3V supply rails to prevent digital switching noise from coupling into the analog front end. Estimated: at 150 mW dissipation and 31 C/W theta_JA, junction temperature rise is approximately 4.6 C above ambient, well within the 150 C maximum - no heatsink required.
Drive the analog inputs (INA+/INA-, INB+/INB-) with a low-impedance differential driver such as the AD8138 or AD8137; single-ended drive is possible but degrades SFDR by 5-10 dB at high input frequencies. According to the Analog Devices datasheet, the ADC's input common-mode voltage must be biased at mid-supply (typically 1.5 V on a 3V rail) using transformer coupling or a dedicated common-mode buffer. Keep input traces matched in length and impedance (100 ohm differential), and route them away from the digital output bus to avoid coupling noise into the analog path.
Do not float the SHDN pin - tie it to DVDD through a 10 kohm resistor if shutdown is not used; otherwise the part may enter an undefined state at power-up. The MUX pin must also be tied high or low explicitly to select between simultaneous and multiplexed sampling modes. According to the Analog Devices datasheet, leaving these configuration pins floating can cause unpredictable output behavior and may also increase supply current by 10-20 mW in some operating modes.
合规信息
RoHS-compliant per the #PBF suffix option on the lead-free variant. Not AEC-Q100 qualified - this is a commercial-grade part. Industrial temperature grade available as LTC2286IUP.
