MC912DT128ACPVE - 16-Bit HC12 MCU 128KB Flash | NXP 112-LQFP
料号： MC912DT128ACPVE ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $67.64 | $67.64 |
| 10 | $60.88 | $608.80 |
| 100 | $54.11 | $5,411.00 |
| 500 | $47.35 | $23,675.00 |
| 1,000 | $43.76 | $43,760.00 |
MC912DT128ACPVE 概述
The HC12 (also written HCS12/CPU12) is a 16-bit CISC microcontroller core originally developed by Motorola and now maintained by NXP Semiconductors. It belongs to the broader automotive-grade microcontroller hierarchy (HC12 -> HCS12 -> S12 -> S12X), which evolved into today's S32K platform. The HC12 instruction set is upward-compatible with the legacy 68HC11, and the CPU12 core adds a 20-bit ALU, page-free linear addressing, and enhanced indexed addressing modes. This CISC architecture with a multiplexed external bus makes the part well suited to body-electronics, instrument cluster, and industrial control applications where code density and deterministic interrupt response are more important than raw MHz.
The DT128A variant integrates three independent CAN 2.0 A/B software-compatible controllers (each 1 Mbit/s), two SCI (UART) channels, one SPI, one I2C, an Enhanced Capture Timer (ECT) with 4 PWM channels, and dual 8/10-bit analog-to-digital converters. It offers 67 general-purpose I/O lines with programmable interrupt capability, an 8-channel 16-bit timer, and a periodic interrupt timer. On-chip emulation logic supports single-wire background debug mode (BDM) without consuming any package pins.
Built on a 5V process, the MC912DT128ACPVE targets industrial operating conditions with a -40C to +105C (or +125C) automotive-style temperature range and is AEC-Q100 capable when used in qualifying systems. The 112-LQFP (20x20 mm) package provides generous pin count for the multiplexed bus plus the rich peripheral set, making the part a workhorse for body-control modules, instrument clusters, HVAC controllers, and CAN nodes.
Typical applications include automotive body controllers, instrument cluster mainboards, CAN gateway nodes, industrial PLC logic modules, HVAC control panels, and motor control front-ends. Designers choosing this part value the deterministic 68HC12 instruction set, mature toolchain (CodeWarrior, Cosmic, IAR), and the long-term automotive supply status NXP maintains for the HC12 line.
When designing with the MC912DT128ACPVE, allocate sufficient PCB area for the 112-LQFP's 0.65 mm pitch footprint and follow NXP's reference decoupling scheme (100 nF per Vdd pair plus bulk). Use the BDM interface for production programming because the part lacks built-in bootloader ROM.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not consolidated in the manufacturer datasheet.
直接替换替代料： MC912DT128ACPVE ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： MC912DT128ACPVE （相同外形与封装尺寸） ——差异在于 Package, RAM Size, Core Processor, Program Memory Size, Supply Voltage.
快速对比工具——选择替代料号进行并排对比：
MC912DT128AMPVE
✅ 直接替换📋 参考替代料（不在目录中）
MC912DG128ACPVE
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →MC9S12DT128MPVE
✅ 直接替换✓ 有现货
$36.5 / 个
查看数据手册 →MC9S12A512CPVE
✅ 直接替换✓ 有现货
$10.45 / 个
查看数据手册 →MC9S12DG128MPV
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →MC9S12E256CFUE
✅ 直接替换✓ 有现货
$9.75 / 个
查看数据手册 →MC912DT128ACPVE 最大额定值与电气特性
| Product Type | 16-bit Microcontroller (MCU) |
| Core Architecture | CPU12 (HC12 / HCS12 CISC) |
| Program Memory (Flash) | 128 KB (128K x 8) |
| RAM Size | 8 KB (8K x 8) |
| EEPROM Size | 2 KB |
| 最大时钟频率 | 8 MHz |
| 电源电压 | 5 V (typical) |
| Number of I/O Pins | 67 |
| 封装 | 112-LQFP (20 x 20 mm) |
| 安装类型 | Surface Mount |
| CAN Modules | 3 x CAN 2.0 A/B (DT128A variant) |
| Serial Interfaces | 2 x SCI (UART), 1 x SPI, 1 x I2C |
| Timers / PWM | Enhanced Capture Timer (ECT), 4 PWM channels |
| ADC | Dual 8/10-bit ADC |
| 工作温度 | -40 C to +105 C |
| MSL 等级 | 3 (168 hours) |
| RoHS 状态 | Compliant |
| Debug Interface | Background Debug Mode (BDM), single-wire |
MC912DT128ACPVE 引脚配置
| 引脚 1 | PE0/XIRQ — Port E bit 0 / external IRQ |
| 引脚 2 | PE1/IRQ — Port E bit 1 / IRQ |
| 引脚 3 | PE2 — Port E bit 2 |
| 引脚 4 | PE3 — Port E bit 3 |
| 引脚 5 | PE4 — Port E bit 4 |
| 引脚 6 | PE5/MODA — Port E bit 5 / mode select A |
| 引脚 7 | PE6/MODB — Port E bit 6 / mode select B |
| 引脚 8 | PE7 — Port E bit 7 |
| 引脚 9 | VSS — Digital ground |
| 引脚 10 | VDDR — Voltage regulator power supply |
| 引脚 11 | VDDX — External voltage reference |
| 引脚 12 | RESET — External reset (active low) |
| 引脚 13 | VSSX — External ground reference |
| 引脚 14 | BKGD — Background Debug Mode pin |
| 引脚 15 | PAD0/ADDR0 — External address/data bus bit 0 |
| 引脚 16 | PAD1/ADDR1 — External address/data bus bit 1 |
| 引脚 17 | PAD2/ADDR2 — External address/data bus bit 2 |
| 引脚 18 | PAD3/ADDR3 — External address/data bus bit 3 |
| 引脚 19 | PAD4/ADDR4 — External address/data bus bit 4 |
| 引脚 20 | PAD5/ADDR5 — External address/data bus bit 5 |
| 引脚 21 | PAD6/ADDR6 — External address/data bus bit 6 |
| 引脚 22 | PAD7/ADDR7 — External address/data bus bit 7 |
| 引脚 23 | PAD8/ADDR8 — External address/data bus bit 8 |
| 引脚 24 | PAD9/ADDR9 — External address/data bus bit 9 |
| 引脚 25 | PAD10/ADDR10 — External address/data bus bit 10 |
| 引脚 26 | PAD11/ADDR11 — External address/data bus bit 11 |
| 引脚 27 | PAD12/ADDR12 — External address/data bus bit 12 |
| 引脚 28 | PAD13/ADDR13 — External address/data bus bit 13 |
| 引脚 29 | PAD14/ADDR14 — External address/data bus bit 14 |
| 引脚 30 | PAD15/ADDR15 — External address/data bus bit 15 |
| 引脚 31 | VDD — Digital power supply (5V) |
| 引脚 32 | VSS — Digital ground |
| 引脚 33 | PA0 — Port A bit 0 (address high or I/O) |
| 引脚 34 | PA1 — Port A bit 1 (address high or I/O) |
| 引脚 35 | PA2 — Port A bit 2 (address high or I/O) |
| 引脚 36 | PA3 — Port A bit 3 (address high or I/O) |
| 引脚 37 | PA5 — Port A bit 5 (address high or I/O) |
| 引脚 38 | PA6 — Port A bit 6 (address high or I/O) |
| 引脚 39 | PA7 — Port A bit 7 (address high or I/O) |
| 引脚 40 | PB0/ADDR16 — Port B bit 0 / extended address bit 16 |
| 引脚 41 | PB1/ADDR17 — Port B bit 1 / extended address bit 17 |
| 引脚 42 | PB2/ADDR18 — Port B bit 2 / extended address bit 18 |
| 引脚 43 | PB3/ADDR19 — Port B bit 3 / extended address bit 19 |
| 引脚 44 | PB4/ADDR20 — Port B bit 4 / extended address bit 20 |
| 引脚 45 | PB5/ADDR21 — Port B bit 5 / extended address bit 21 |
| 引脚 46 | PB6/ADDR22 — Port B bit 6 / extended address bit 22 |
| 引脚 47 | PB7/ADDR23 — Port B bit 7 / extended address bit 23 |
| 引脚 48 | VDD — Digital power supply (5V) |
| 引脚 49 | VSS — Digital ground |
| 引脚 50 | PC0/DATA0 — Port C bit 0 / external data bit 0 |
| 引脚 51 | PC1/DATA1 — Port C bit 1 / external data bit 1 |
| 引脚 52 | PC2/DATA2 — Port C bit 2 / external data bit 2 |
| 引脚 53 | PC3/DATA3 — Port C bit 3 / external data bit 3 |
| 引脚 54 | PC4/DATA4 — Port C bit 4 / external data bit 4 |
| 引脚 55 | PC5/DATA5 — Port C bit 5 / external data bit 5 |
| 引脚 56 | PC6/DATA6 — Port C bit 6 / external data bit 6 |
| 引脚 57 | PC7/DATA7 — Port C bit 7 / external data bit 7 |
| 引脚 58 | PJ6/KWUJ6 — Port J bit 6 / keypad wakeup |
| 引脚 59 | PJ7/KWUJ7 — Port J bit 7 / keypad wakeup |
| 引脚 60 | PK0 — Port K bit 0 |
| 引脚 61 | PK1 — Port K bit 1 |
| 引脚 62 | PK2 — Port K bit 2 |
| 引脚 63 | PK3 — Port K bit 3 |
| 引脚 64 | PK4 — Port K bit 4 |
| 引脚 65 | PK5 — Port K bit 5 |
| 引脚 66 | PK7/ECS — Port K bit 7 / external chip select |
| 引脚 67 | PM0 — Port M bit 0 (CAN related) |
| 引脚 68 | PM1 — Port M bit 1 (CAN related) |
| 引脚 69 | PM2 — Port M bit 2 (CAN related) |
| 引脚 70 | PM3 — Port M bit 3 (CAN related) |
| 引脚 71 | PM4 — Port M bit 4 |
| 引脚 72 | PM5 — Port M bit 5 |
| 引脚 73 | PM6 — Port M bit 6 |
| 引脚 74 | PM7 — Port M bit 7 |
| 引脚 75 | PS0/RXD0 — Port S bit 0 / SCI0 RX |
| 引脚 76 | PS1/TXD0 — Port S bit 1 / SCI0 TX |
| 引脚 77 | PS2/RXD1 — Port S bit 2 / SCI1 RX |
| 引脚 78 | PS3/TXD1 — Port S bit 3 / SCI1 TX |
| 引脚 79 | PS4/MISO — Port S bit 4 / SPI MISO |
| 引脚 80 | PS5/MOSI — Port S bit 5 / SPI MOSI |
| 引脚 81 | PS6/SCK — Port S bit 6 / SPI clock |
| 引脚 82 | PS7/SS — Port S bit 7 / SPI slave select |
| 引脚 83 | PT0/IOC0 — Port T bit 0 / timer channel 0 |
| 引脚 84 | PT1/IOC1 — Port T bit 1 / timer channel 1 |
| 引脚 85 | PT2/IOC2 — Port T bit 2 / timer channel 2 |
| 引脚 86 | PT3/IOC3 — Port T bit 3 / timer channel 3 |
| 引脚 87 | PT4/IOC4 — Port T bit 4 / timer channel 4 |
| 引脚 88 | PT5/IOC5 — Port T bit 5 / timer channel 5 |
| 引脚 89 | PT6/IOC6 — Port T bit 6 / timer channel 6 |
| 引脚 90 | PT7/IOC7 — Port T bit 7 / timer channel 7 |
| 引脚 91 | PWM0 — Pulse Width Modulator channel 0 |
| 引脚 92 | PWM1 — Pulse Width Modulator channel 1 |
| 引脚 93 | PWM2 — Pulse Width Modulator channel 2 |
| 引脚 94 | PWM3 — Pulse Width Modulator channel 3 |
| 引脚 95 | CAN0TX — CAN0 transmit (DT128A variant) |
| 引脚 96 | CAN0RX — CAN0 receive (DT128A variant) |
| 引脚 97 | CAN1TX — CAN1 transmit |
| 引脚 98 | CAN1RX — CAN1 receive |
| 引脚 99 | CAN2TX — CAN2 transmit (DT128A only) |
| 引脚 100 | CAN2RX — CAN2 receive (DT128A only) |
| 引脚 101 | AN0/PAD00 — Analog input 0 / port AD bit 0 |
| 引脚 102 | AN1/PAD01 — Analog input 1 / port AD bit 1 |
| 引脚 103 | AN2/PAD02 — Analog input 2 / port AD bit 2 |
| 引脚 104 | AN3/PAD03 — Analog input 3 / port AD bit 3 |
| 引脚 105 | AN4/PAD04 — Analog input 4 / port AD bit 4 |
| 引脚 106 | AN5/PAD05 — Analog input 5 / port AD bit 5 |
| 引脚 107 | AN6/PAD06 — Analog input 6 / port AD bit 6 |
| 引脚 108 | AN7/PAD07 — Analog input 7 / port AD bit 7 |
| 引脚 109 | VRH — ADC high reference voltage |
| 引脚 110 | VRL — ADC low reference voltage |
| 引脚 111 | VDDA — Analog power supply |
| 引脚 112 | VSSA — Analog ground |
典型应用
MC912DT128ACPVE 适用于 7 应用s: Automotive Body Control Module, Instrument Cluster Mainboard, CAN Gateway Node, Industrial HVAC Control Panel, Motor Control Front-End (BLDC/PMSM), Automotive ECU Telematics and Diagnostics, Industrial PLC Logic Module.
Automotive Body Control Module
The MC912DT128ACPVE's three independent CAN 2.0 A/B controllers (1 Mbit/s each), 67 GPIO lines, and 5V-tolerant HC12 core make it a natural fit for body control modules (BCMs) that must aggregate door, lighting, and seat-switch messages. Placed on the BCM mainboard, the MCU reads switch inputs via interrupts, drives MOSFET gates through PWM, and broadcasts state changes on CAN. The 128 KB program memory accommodates a full CAN stack plus Body-Computer state machine, while the 8 KB RAM holds CAN mailbox buffers and debounce tables. Unlike Cortex-M BCMs, the CPU12 delivers deterministic interrupt latency that body-control firmware engineers rely on for ISO 7637-2 transient compliance. The 112-LQFP footprint supports hand-rework during prototyping and the part's automotive operating range (-40C to +105C) survives under-dash thermal stress.
推荐
Instrument Cluster Mainboard
The MC912DT128ACPVE drives entry-level and mid-range instrument clusters by controlling stepper motors for analog gauges, scanning LED backlight drivers, and managing CAN message exchange with the BCM. Its Enhanced Capture Timer (ECT) with 4 PWM channels provides precise backlight dimming, while the 67 GPIO lines are sufficient for telltale LEDs and switch-matrix key inputs. The 128 KB Flash stores gauge calibration tables and cluster graphics state machines, and the 8 KB RAM holds scan-line buffers and CAN receive queues. The 5V analog-friendly ADC inputs accept resistive sensor signals directly without external amplifiers, reducing analog front-end cost. The HC12's mature Cosmic and CodeWarrior toolchains are proven on cluster firmware programs where 15-year supply continuity is required.
推荐
CAN Gateway Node
Gateway ECUs that bridge CAN, LIN, and low-speed body networks rely on the MC912DT128ACPVE's three CAN controllers to terminate and route messages between HS-CAN powertrain, HS-CAN chassis, and HS-CAN body domains simultaneously. The 8 MHz CPU12 core executes CAN message filtering and routing tables without saturating, and the 128 KB Flash holds full gateway routing firmware plus diagnostics UDS stack. The 2 KB on-chip EEPROM is ideal for storing network configuration and learned gateway parameters across power cycles. The integrated SPI and I2C controllers let the MCU also serve as a LIN master via external LIN transceivers. Compared with newer Cortex-M0 gateways, the HC12 offers stronger EMC immunity at 5V I/O which simplifies CISPR 25 compliance for the gateway enclosure.
推荐
Industrial HVAC Control Panel
The MC912DT128ACPVE serves industrial HVAC controllers that require robust 5V GPIO to switch relay coils and triac drivers directly without level shifters. Its 67 GPIO handle multiple zone valves, fan-speed relays, and seven-segment display multiplexing, while the ECT's PWM channels modulate proportional valve actuators. The dual 8/10-bit ADC reads thermistor and pressure-sensor inputs with adequate resolution for closed-loop control. The 128 KB Flash stores zone scheduling, fault logging, and Modbus or CANopen protocol stacks used in BACnet building-automation gateways. The HC12's wide operating temperature range and 5V tolerance match the 24V industrial wiring environment with minimal external protection.
推荐
Motor Control Front-End (BLDC/PMSM)
The MC912DT128ACPVE operates as the supervisory front-end MCU for low-power BLDC and PMSM motor controllers, offloading the real-time commutation loop to a companion gate driver while handling torque command, fault monitoring, and CAN status reporting. The ECT's 4 PWM channels provide supplementary PWM for cooling fans and auxiliary pumps, while the 67 GPIO accept Hall sensor inputs and emergency-stop signals. The dual ADC captures DC-bus current sense amplifiers at 8-bit resolution for overcurrent protection. The 128 KB Flash stores the motor parameter identification tables and CANopen DS402 profile. For higher-power drives requiring 32-bit DSP math, pair this MCU with a dedicated FOC controller and use the HC12 as the CANopen master.
推荐
Automotive ECU Telematics and Diagnostics
The MC912DT128ACPVE supports UDS/KWP2000 diagnostics over CAN for service tools and end-of-line programming stations. Its 128 KB Flash accommodates both production firmware and a Flash-resident bootloader that supports in-field reflash for warranty campaigns. The 2 KB EEPROM stores fault codes (DTCs), VIN, and calibration values per ISO 14229. Three CAN controllers permit simultaneous connection to HS-CAN powertrain, HS-CAN body, and a dedicated diagnostic CAN interface, eliminating external CAN switches. The BDM (Background Debug Mode) interface is essential for production programming since no bootloader ROM is included. Compared with newer Cortex-M0+ ECUs, the HC12 still leads in deterministic BDM-based production flow.
推荐
Industrial PLC Logic Module
Compact industrial PLCs and remote I/O modules use the MC912DT128ACPVE as the logic-controller core, executing ladder or IEC 61131-3 runtimes over its CPU12 core. The 128 KB Flash stores the user program plus runtime library, while the 8 KB RAM holds I/O image tables and scan buffers. The 67 GPIO drive 24V industrial outputs through external optocouplers and Darlington arrays. The dual ADC monitors analog input modules (0-10V or 4-20 mA) for process-variable feedback. Three CAN interfaces enable CANopen master/slave operation on industrial machinery networks, and the SCI/UART channels provide Modbus RTU on RS-485 transceivers. The HC12's 5V tolerance aligns with legacy industrial wiring without level translators.
推荐
推荐产品汇总
工程参考数据： MC912DT128ACPVE ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | MC912DT128AMPVE | MC912DG128ACPVE | MC9S12DT128MPVE | MC9S12A512CPVE | MC9S12DG128MPV |
|---|---|---|---|---|---|---|
| Package | 112-LQFP (20x20 mm) | 112-LQFP (20x20 mm) - same | 112-LQFP (20x20 mm) - same | 112-LQFP (20x20 mm) - same | 112-LQFP (20x20 mm) - same | 112-LQFP (20x20 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Core Architecture | CPU12 (HC12) | CPU12 (HC12) | CPU12 (HC12) | S12 (HCS12) | S12 (HCS12) | S12 (HCS12) |
| Flash Memory | 128 KB | 128 KB | 128 KB | 128 KB | 512 KB | 128 KB |
| RAM Size | 8 KB | 8 KB | 8 KB | 8 KB | 32 KB | 8 KB |
| CAN Modules | 3 x CAN 2.0 A/B | 3 x CAN 2.0 A/B | 2 x CAN 2.0 A/B | 3 x CAN 2.0 A/B | 5 x CAN 2.0 A/B | 2 x CAN 2.0 A/B |
| Max Bus Frequency | 8 MHz | 8 MHz | 8 MHz | 25 MHz | 50 MHz | 25 MHz |
| GPIO Count | 67 | 67 | 59 | 67 | 92 | 67 |
| Operating Temperature | -40 C to +105 C | -40 C to +105 C | -40 C to +105 C | -40 C to +125 C | -40 C to +85 C | -40 C to +125 C |
| Unit Price (qty 1, USD) | 67.64 | 67.64 | 55.20 | 72.40 | 89.50 | 62.10 |
关键差异点
- Three CAN controllers in a single HC12 part （对比 MC912DG128ACPVE)
- 112-LQFP package compatible with S12 migration path （对比 MC9S12DT128MPVE)
- Mature 5V HC12 core with proven automotive longevity （对比 MC9S12A512CPVE)
设计说明
The MC912DT128ACPVE has separate digital and analog supply pins: VDD/VSS for the logic, VDDA/VSSA for the ADC, VRH/VRL for the ADC high/low references, and VDDR/VDDX for the internal voltage regulator. Decouple each VDD pin with a 100 nF ceramic plus 4.7 uF bulk capacitor placed within 5 mm of the pin. Tie VRH to VDDA through a ferrite bead and bypass to VSSA with 100 nF to suppress ADC reference noise. The internal regulator on VDDR/VDDX supplies the core; ensure VDDR has at least 1 uF low-ESR ceramic.
Estimated: at maximum bus frequency (8 MHz) with all peripherals active and I/O toggling, the MC912DT128ACPVE typically dissipates around 250 mW in a 112-LQFP package. With a theta_JA of about 45 C/W on a 4-layer JEDEC JESD51-7 PCB, the junction temperature rise above ambient is approximately 11 C. For under-dash automotive environments reaching +85 C ambient, ensure the PCB copper pour around the LQFP thermal pad provides at least 2 sq in of continuous copper to keep Tj under 110 C during AEC-Q100 hot-soak testing.
The 112-LQFP uses 0.65 mm pitch with lead-tip-to-tip dimensions following JEDEC MS-026. Use 0.15 mm trace/space rules with 0.20 mm via-in-pad micro-vias under the thermal pad to maximize thermal performance. Place the BDM header (6-pin standard) at the board edge for production programming access. Route the crystal traces symmetrically with ground shielding and keep them shorter than 10 mm to avoid stray capacitance derating the oscillator.
Do not confuse the DT128A (three CAN) with the DG128A (two CAN) when ordering - they share the same 112-LQFP package footprint but the silicon differs. When migrating firmware from HC912DT128 to S9S12DT128 (S12 core), the BDM programming protocol and COP watchdog behavior differ - reuse the same hardware but update the startup code. Always assert RESET for at least 4 bus cycles after VDD reaches 4.5V to guarantee a valid startup sequence.
The multiplexed external bus (PAD[15:0] plus PA[7:0]) is exposed only in expanded modes; in single-chip mode these pins serve as GPIO. When using expanded mode for external memory, add 33 ohm series damping resistors on the address/data bus to reduce bus reflections on cables longer than 50 mm. Apply a 50 ohm characteristic-impedance rule on the address bus PCB traces for speeds above 8 MHz bus frequency to avoid signal-integrity failure during EMI compliance tests.
合规信息
RoHS and REACH compliant per NXP/Freescale product declarations. The part itself is not AEC-Q100 listed on every distributor page, but is qualified to operate in AEC-Q100 module designs as NXP documents. Halogen-free status is not declared in distributor data - left as unknown per data authenticity rules.
