MM5625-01NDB-TR - Dual DP3T 80Gbps Loopback Switch | Menlo Micro

Semiconductor Final Test (ATE)

The MM5625-01NDB-TR is purpose-built for automated test equipment final test, where it routes high-speed differential channels between the device-under-test and the tester pin electronics. Its dual DP3T topology enables AC-coupled loopback connections that close the SerDes channel locally on the load board, letting one tester resource validate transmit and receive paths in parallel. According to the Menlo Micro datasheet, the 80 Gbps / 20 GHz capability covers PCIe Gen 5/6 and multi-lane SerDes devices, while the greater than 3 billion switching cycles eliminate the relay-wear bottleneck of mechanical solutions. The fully integrated driver and charge pump, SPI-controlled by the tester host processor, removes the discrete relay-driver circuitry that typically consumes load-board area and complicates signal-integrity routing in space-constrained final test sockets.

Wafer Sort / Probe Test

In probe test and wafer sort, the MM5625 provides the parallel-testing density demanded by space-constrained probe-card and probe-board designs. Menlo Micro states the MM5625 enables unprecedented levels of parallel testing for probe test environments, where channel count per square millimeter directly determines test throughput and cost per die. Its 8.2 mm x 8.2 mm 226-LGA footprint consolidates what previously required banks of mechanical relays and their driver ICs, shortening differential stubs and preserving signal integrity at 20 GHz bandwidth. The AC-coupled differential paths are compatible with the AC-blocking capacitors already present in SerDes test channels, so integration requires no DC-path redesign. Solid-state Ideal Switch technology also avoids the contact bounce and microphonics that mechanical relays introduce during high-speed AC measurements at the wafer level.

PCIe Gen 5 / Gen 6 Compliance Testing

PCIe Gen 5 (32 GT/s) and Gen 6 (64 GT/s) compliance and characterization testing require loopback paths with bandwidth well beyond the Nyquist frequency of the data rate. The MM5625's 20 GHz bandwidth and 80 Gbps capability provide margin over both standards, per Menlo Micro's product documentation, allowing the same switch fabric to serve multiple test platforms. In a typical bench or ATE setup, the dual DP3T switch selects between a through path to the DUT and a loopback path that returns the transmitter output to the receiver input, enabling eye-margin and BER measurement without moving cables. Because the device is SPI-controlled with 7 control lines and an integrated charge pump, test executives can reconfigure the signal routing in software with fast, repeatable switching - a requirement for automated compliance runs with thousands of iterations.

Smartphone and Graphics Processor Test

Application processors for smartphones and modern GPUs integrate dozens of high-speed SerDes lanes - MIPI, UFS, PCIe, and custom interfaces - all of which need loopback validation at production test. The MM5625 addresses this segment explicitly: Menlo Micro lists chip testing for smartphones and graphics processors among its primary applications. Each 8.2 mm x 8.2 mm dual DP3T site handles two differential triple-throw channel groups, so a 16-site load board can realize dense per-site loopback with far fewer switch packages than relay-based designs. The greater than 3 billion cycle lifetime matters here because high-volume consumer silicon runs continuous production for years; the switch must outlast the tester. The industrial temperature grade accommodates the elevated ambient temperatures inside test handlers without derating the RF performance of the AC-coupled loopback channels.

High-Speed Memory and AI Accelerator Test

High-bandwidth memory interfaces and AI accelerator SerDes fabrics now operate in the tens of Gbps per lane, demanding loopback switches that neither limit the channel eye nor add measurable jitter. The MM5625's Ideal Switch technology provides the low insertion loss and fast switching speed cited in the Menlo Micro datasheet, and its listing explicitly targets high-speed memory and accelerator products. In accelerator production test, per-package the switch is placed between the tester card and the device socket, selecting loopback versus open/short path configurations under SPI control. Its 80 Gbps rating covers current HBM-adjacent SerDes and next-generation 224G-class development channels partially, though designers targeting beyond-80G serial links should verify margins against the full datasheet S-parameter data. The SiP integration reduces the load-board component count, improving yield and rework statistics on dense, high-value test boards.

Network Processor Test Systems

Network processors and switch silicon carry many lanes of 25G-to-112G SerDes, and their production test requires a routing fabric that scales lane count while holding signal integrity. The MM5625 is named by Menlo Micro as a solution for network processor chip testing. Its AC-coupled dual DP3T channels integrate cleanly into multi-site test heads: the SPI control bus allows a single host processor to address many MM5625 sites, and the integrated charge pump removes the high-voltage gate-drive supplies that discrete FET switch matrices require. Compared with electromechanical relays, the solid-state switch eliminates actuation delays from the test time budget, since switching speed is a semiconductor figure rather than a mechanical one. This directly increases tester utilization on high-mix networking product lines where each DUT touches hundreds of differential lanes.