PCA9527DP,118 - 3-Ch I2C/HDMI DDC CEC Bus Buffer | NXP
料号： PCA9527DP,118 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0.95 | $0.95 |
| 10 | $0.86 | $8.60 |
| 100 | $0.72 | $72.00 |
| 500 | $0.61 | $305.00 |
| 1,000 | $0.52 | $520.00 |
PCA9527DP,118 概述
A bus buffer (also called a bus extender or repeater) is an interface IC inserted in series with a two-wire serial bus such as I2C (Inter-Integrated Circuit) or SMBus (System Management Bus). Within the broader hierarchy of interface semiconductors, bus buffers sit alongside level translators and line drivers, and their role is to segment bus capacitance, regenerate signal edges, and isolate parasitic loading so the bus can be longer or drive more devices than the raw open-drain bus standard would otherwise permit.
Key features of the PCA9527 include three independent bidirectional channels dedicated to the HDMI Display Data Channel (DDC) clock and data lines plus the Consumer Electronics Control (CEC) line, support for Fast-mode 400 kHz I2C and SMBus signaling, an active-HIGH EN enable pin with an internal pull-up of approximately 100 kOhm to VCC(B) that places the device in a low-power down state when disabled, and two separate power supply pins that allow voltage level shifting between the two sides of the bus.
Technically, the device uses rise-time accelerators on each open-drain channel to actively speed up rising edges that would otherwise be limited by pull-up resistors and bus capacitance. Input capacitance is 8 pF per pin, minimizing loading on the source side, and supply current is specified up to 100 mA. Because the channels are bidirectional and open-drain, no direction-control signal is required, which is essential for the acknowledge-clock-stretching behavior of I2C and DDC.
Typical applications are HDMI source, sink, repeater, and switch designs where DDC and CEC lines must be buffered between the HDMI connector and an HDMI processor, EDID EEPROM access circuits, set-top boxes, TVs, AV receivers, and projectors. The buffered DDC prevents a hot-plugged HDMI cable's cable capacitance from corrupting EDID reads, while CEC buffering preserves the single-wire control channel integrity.
A key design consideration: connect the EN pin to VCC(B) if the buffer should be always active, and remember that re-enabling introduces a recovery delay, so power sequencing of the two supply pins matters in hot-plug HDMI systems.
This page synthesizes distributor pricing tiers, drop-in alternative options, and practical HDMI DDC design notes that are not consolidated in the manufacturer datasheet.
直接替换替代料： PCA9527DP,118 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： PCA9527DP,118 （相同外形与封装尺寸） ——差异在于 Package.
快速对比工具——选择替代料号进行并排对比：
PCA9517ADP,118
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
PCA9515BDP,118
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
NVT2002DP,118
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$0.19 / 个
查看数据手册 →PCA9527DP,118 规格参数
| 功能 | 3-channel bidirectional open-drain bus buffer |
| Bus Type | I2C-bus, SMBus, HDMI DDC, CEC |
| Number of Channels | 3 |
| Maximum Bus Frequency | 400 kHz |
| Propagation Delay Time | 115 ns |
| Supply Voltage Range | 2.7 V to 5.5 V |
| Supply Current (max) | 100 mA |
| 输入电容 | 8 pF |
| 输出类型 | Open-drain with rise-time accelerator |
| 使能引脚 | EN, active-HIGH, internal ~100 kOhm pull-up to VCC(B) |
| Level Shifting | Yes, via two separate supply pins (VCC(A) / VCC(B)) |
| 封装 | 10-TSSOP / 10-TFSOP, 0.118 inch body width |
| 安装类型 | Surface Mount |
| Packing Suffix | ,118 = Tape & Reel, moisture barrier |
| RoHS 状态 | Compliant (per JLCPCB listing) |
| Application | HDMI DDC clock/data and CEC buffering |
PCA9527DP,118 10-tssop / 10-tfsop, 0.118 inch body width 引脚配置指南
PCA9527DP,118（10-tssop / 10-tfsop, 0.118 inch body width 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： PCA9527DP,118.
请参阅 数据手册 以查看完整引脚配置。
典型应用
PCA9527DP,118 适用于 6 应用s: HDMI Source Devices (Set-Top Boxes, Players), HDMI Sink Devices (TVs, Monitors, Projectors), AV Receivers and HDMI Switches, EDID EEPROM Access Circuits, I2C-bus and SMBus Segmentation, HDMI Repeater and Extender Designs.
HDMI Source Devices (Set-Top Boxes, Players)
In HDMI source equipment such as set-top boxes, Blu-ray players, and media streamers, the PCA9527DP,118 buffers the DDC SDA/SCL pair and the CEC line between the processor and the HDMI connector. The processor-side bus sees only 8 pF input capacitance per pin instead of the full cable-plus-connector capacitance, which is what allows reliable 100 kHz EDID reads over hot-plugged cables of unknown length. The two supply pins (2.7 V to 5.5 V per side) translate between a 5 V EDID EEPROM segment and a 3.3 V HDMI processor segment without discrete MOSFET translator circuits. Rise-time accelerators restore Fast-mode-capable edges, and the EN pin can be driven by hot-plug detect so the buffer is powered down when no cable is attached, saving power and preventing bus contention during connector events.
推荐
HDMI Sink Devices (TVs, Monitors, Projectors)
HDMI sink equipment such as flat-panel TVs, monitors, and projectors must read the source's EDID over DDC while simultaneously exposing their own EDID EEPROM, and must terminate the CEC line. The PCA9527DP,118 isolates the HDMI connector capacitance from the internal EDID memory bus, letting designers place multiple HDMI inputs on segmented DDC buses without cumulative capacitance failures. The 3-channel architecture covers SDA, SCL, and CEC in one TSSOP-10 footprint, which is valuable near the dense connector area of multi-input TVs. Supply current is bounded at 100 mA maximum, and the open-drain bidirectional nature preserves the clock-stretching and arbitration behavior inherent to I2C/DDC, so EDID acknowledge cycles pass through transparently at 400 kHz capability even though DDC operates at 100 kHz.
推荐
AV Receivers and HDMI Switches
AV receivers and HDMI switchers fan out several HDMI inputs to one output; each input's DDC and CEC must be buffered independently so a disconnected or high-capacitance cable does not hang the shared control bus. Using one PCA9527DP,118 per HDMI port gives clean per-port isolation: the EN pin ties to that port's hot-plug detect, power-down state reduces quiescent load, and the 115 ns delay is negligible against 100 kHz DDC timing (4.6 us period). The internal ~100 kOhm EN pull-up defaults the channel active if the detect signal is missing, and the accelerator circuitry keeps EDID read rise times compliant even on 15 m cables. The TSSOP-10, 0.118 inch body fits the tight connector field of 4-to-8-input switcher boards.
推荐
EDID EEPROM Access Circuits
Systems that emulate or capture EDID - such as KVM extenders, video wall controllers, and test instruments - place an EEPROM behind a buffered DDC segment. The PCA9527DP,118 separates the volatile external DDC bus from the local EEPROM bus so the EEPROM can be rewritten at full 400 kHz Fast-mode speed by a management controller while the HDMI source sees a stable, cable-independent DDC. Input capacitance of 8 pF keeps the isolated segment light, and the two supply pins allow a 5 V EEPROM on one side and a 3.3 V controller on the other. Designers should keep the NR-side pull-ups sized for the EEPROM segment and verify rise time at 400 kHz, since the accelerator assists but does not replace external resistive pull-ups on open-drain channels.
推荐
I2C-bus and SMBus Segmentation
Beyond HDMI, the PCA9527DP,118 serves as a general 3-channel I2C-bus/SMBus buffer for segmenting heavily loaded system management buses. SMBus cards, backplanes, and server chassis accumulate capacitance from many device inputs; inserting the buffer splits the bus into low-capacitance segments, each of which meets rise-time limits with standard pull-ups. The 2.7 V to 5.5 V supply range covers 3.3 V and 5 V logic domains, and the two-supply-pin architecture provides level shifting between mixed-voltage segments. Because all three channels are bidirectional open-drain, SMBus ARP, PEC, and clock-low-extend behaviors pass through unchanged. The EN pin allows a management controller to gate a segment off during fault isolation, and the power-down state on disable reduces standby current in always-on infrastructure equipment.
推荐
HDMI Repeater and Extender Designs
HDMI repeaters, baluns, and extenders regenerate the TMDS video lanes and must also rebuild the DDC and CEC channels across isolation or cable stages. The PCA9527DP,118 buffers DDC/CEC on each side of the repeater, ensuring EDID negotiation completes before video link training and keeping CEC control latency low - the 115 ns buffer delay is trivial compared with CEC bit timing. The accelerator feature is particularly useful after galvanic isolation or long extension runs where edges arrive degraded. Its 8 pF input capacitance minimizes loading on the incoming cable, and the active-HIGH EN with ~100 kOhm pull-up can be sequenced from the repeater's hot-plug state machine so that the downstream DDC activates only after upstream EDID capture, preventing enumeration contention during hot-plug events.
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推荐产品汇总
工程参考数据： PCA9527DP,118 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | PCA9517ADP,118 | PCA9515BDP,118 | NVT2002DP,118 |
|---|---|---|---|---|
| Package | 10-TSSOP (0.118 in) | 10-TSSOP - same footprint | 10-TSSOP - same footprint | TSSOP-10 - same footprint |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Channel Count | 3 | 2 | 2 | 2 |
| Function | Bidirectional buffer + accelerator | Level-translating buffer | Non-translating buffer | Level translator (no accelerator) |
| CEC Channel Support | Yes (dedicated 3rd channel) | No | No | No |
关键差异点
- Dedicated 3rd channel for HDMI CEC （对比 PCA9517ADP,118)
- Rise-time accelerators for Fast-mode 400 kHz （对比 NVT2002DP,118)
- Two-supply-pin level shifting with power-down enable （对比 PCA9515BDP,118)
设计说明
Place the PCA9527DP,118 within 20-30 mm of the HDMI connector so the high-capacitance cable side is confined to the short stub between connector and buffer. Route the three buffered channels (SDA, SCL, CEC) with ground return vias nearby; the channels are open-drain so pull-up resistor placement on both A and B segments directly determines rise time. Keep the 8 pF input-capacitance side trace stubs short to preserve the isolation benefit that justifies the buffer.
The device has two independent supply pins (VCC(A), VCC(B)), each within 2.7 V to 5.5 V. Decouple each pin with a 100 nF ceramic capacitor placed within 2 mm of the pin. Maximum supply current is specified at 100 mA, so size the local rail accordingly (estimated: at 3.3 V the worst-case rail load is about 0.33 W per side). Remember the EN pin references VCC(B) through an internal ~100 kOhm pull-up - drive it from logic referenced to the B-side domain only.
Two common HDMI pitfalls: (1) driving EN from the wrong supply domain - the pull-up ties to VCC(B), so a floating B-side supply can leave the buffer in an indeterminate state during hot-plug; (2) expecting instant re-activation - the datasheet states that disabling puts the device in a power-down state with a recovery delay, so hot-plug state machines must wait before assuming DDC is live after re-enable. Also do not substitute a 2-channel buffer (PCA9515B/9517A) into the PCA9527 footprint without rerouting CEC, since those parts lack the third channel.
合规信息
RoHS compliance confirmed via JLCPCB part listing. REACH, halogen-free, and conflict-minerals status not stated in retrieved data - confirm via NXP material declaration.
