PN5120A0HN1/C2,118 - Full NFC Frontend 13.56MHz QFN-32 | NXP
料号： PN5120A0HN1-C2118 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $4.92 | $4.92 |
| 10 | $4.43 | $44.30 |
| 100 | $3.94 | $394.00 |
| 500 | $3.55 | $1,775.00 |
| 1,000 | $3.16 | $3,160.00 |
PN5120A0HN1-C2118 概述
An NFC frontend is the analog/digital interface block that drives the antenna, demodulates the inductively-coupled load modulation from a contactless card or peer device, and presents decoded frames to a host controller through a standard digital interface. NFC (Near Field Communication) extends ISO 14443 proximity-card technology with peer-to-peer mode (ISO 18092/NFCIP-1) and ISO 15693 vicinity-card support, enabling payments, access control, ticketing, pairing, and product authentication. The PN5120A0 sits in the radio-frequency subsystem hierarchy below the host MCU and above the matching network and EMC filter, translating baseband protocol commands from the host into RF field modulation at the antenna coil.
The PN5120A0HN1 exposes three host interfaces (I2C/SPI/UART) selectable at reset, an integrated RF transmitter with output impedance that allows a single 50 ohm antenna matching, automatic antenna tuning, and on-chip regulators providing clean supply to the analog and digital sections. Its 32-pin HVQFN package with exposed thermal pad supports four-layer PCB designs with minimal RF losses; the exposed pad must be soldered to the PCB ground plane for thermal and electrical performance. Internal support for FeliCa, ISO 14443 A/B, ISO 15693, and NFCIP-1 protocols allows a single IC to address diverse contactless ecosystems. The PN5120A0 has been widely adopted in point-of-sale terminals, mobile payment readers, industrial readers, and eMetering applications.
Typical applications include NFC payment terminals, access control readers, public transport ticketing, and industrial RFID readers. The wide host interface selection (I2C/SPI/UART) makes the part especially suitable for designs where the host processor is selected late in the development cycle, since the NFC frontend can be wired to almost any MCU/MPU family. Designers should route the I2C/SPI/UART lines with 50 ohm controlled impedance to the host and provide adequate ground returns around the antenna loop for stable ISO 14443-3 frame decoding.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： PN5120A0HN1-C2118 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
PN5120A0HN1/C2,151
✅ 直接替换📋 参考替代料（不在目录中）
PN5120A0HN1/C2,125
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
PN5120A0ET/C2,118
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
CLRC66303HN,151
✅ 直接替换📋 参考替代料（不在目录中）
MFRC63002HN,151
✅ 直接替换📋 参考替代料（不在目录中）
MFRC52202HN1,118
✅ 直接替换📋 参考替代料（不在目录中）
PN5120A0HN1-C2118 规格参数
| Product Type | NFC/RFID frontend IC |
| Carrier Frequency | 13.56 MHz |
| Supported Protocols | FeliCa, ISO 14443 A/B, ISO 15693, MIFARE, NFCIP-1 |
| Host Interfaces | I2C, SPI, UART (selectable) |
| Supply Voltage Range | 2.5 V to 3.6 V |
| Data Mode Detector | Integrated (auto protocol identification) |
| 封装 | HVQFN-32 with exposed pad |
| 引脚数量 | 32 |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| MSL 等级 | 3 |
PN5120A0HN1-C2118 引脚配置
| 引脚 1 | GND — Ground reference |
| 引脚 2 | ANT1 — Antenna connection 1 |
| 引脚 3 | ANT2 — Antenna connection 2 |
| 引脚 4 | VCC — Supply voltage (2.5-3.6 V) |
| 引脚 5 | RX — Receiver analog input |
| 引脚 6 | TX1 — Transmitter output 1 |
| 引脚 7 | TX2 — Transmitter output 2 |
| 引脚 8 | SVDD — Supply voltage for analog section |
| 引脚 9 | AVSS — Analog ground |
| 引脚 10 | AUX — Auxiliary ADC input |
| 引脚 11 | AVDD — Analog supply (regulated output) |
| 引脚 12 | DVDD — Digital supply (regulated output) |
| 引脚 13 | DVSS — Digital ground |
| 引脚 14 | RST — Reset input (active low) |
| 引脚 15 | IRQ — Interrupt request to host |
| 引脚 16 | SCL — I2C clock / SPI clock |
| 引脚 17 | SDA — I2C data / SPI MOSI/MISO |
| 引脚 18 | I2C_ADDR — I2C address strap |
| 引脚 19 | IFSEL0 — Interface mode select bit 0 |
| 引脚 20 | IFSEL1 — Interface mode select bit 1 |
| 引脚 21 | OSC_IN — 27.12 MHz crystal input |
| 引脚 22 | OSC_OUT — 27.12 MHz crystal output |
| 引脚 23 | CLK_OUT — Host reference clock output |
| 引脚 24 | TX_PWR — Transmitter power control |
| 引脚 25 | RX_AMP — Receiver amplifier control |
| 引脚 26 | DEMOD — Demodulator bias |
| 引脚 27 | PWR — Power management control |
| 引脚 28 | TEST1 — Test mode input 1 (tie to GND in production) |
| 引脚 29 | TEST2 — Test mode input 2 (tie to GND in production) |
| 引脚 30 | NC — Not connected (per datasheet) |
| 引脚 31 | NC — Not connected (per datasheet) |
| 引脚 32 | EPAD — Exposed thermal pad - must solder to PCB ground |
典型应用
PN5120A0HN1-C2118 适用于 7 应用s: NFC Payment Terminal (POS), Access Control Reader (Door/Barrier), Public Transport Ticketing Validator, Industrial RFID Reader (ISO 15693), NFC Peer-to-Pairing & IoT Provisioning, eMetering & Wireless Sensor Networks, Printer & Consumable Authentication.
NFC Payment Terminal (POS)
The PN5120A0's 13.56 MHz carrier and ISO 14443 A/B/MIFARE support make it ideal for contactless payment terminals where transaction latency and EMVCo compliance matter. The device's integrated data mode detector decodes incoming card frames automatically, offloading the host MCU. With 2.5-3.6 V supply it pairs directly with battery-backed POS peripherals, and the I2C/SPI/UART interface selection allows late-binding to a secure-element MCU. Compared to discrete RF frontends it shrinks BOM and certification effort.
推荐
Access Control Reader (Door/Barrier)
The PN5120A0HN1/C2,118 fits door-entry readers thanks to its multi-protocol ISO 14443/15693/MIFARE support on a single IC, reducing SKU complexity for sites mixing contactless badges and mobile credentials. Its high receiver sensitivity extends read range beyond 5 cm at door-mount distances, and the integrated data mode detector identifies credential type on every tap. The 32-pin HVQFN exposed-pad package supports slim reader housings. Pair with a small Cortex-M0 host running OSDP over RS-485.
推荐
Public Transport Ticketing Validator
FeliCa and ISO 14443 dual-protocol support on the PN5120A0HN1 enables validators that accept both Japanese FeliCa transit cards and European/Asian contactless tickets on the same antenna. The integrated protocol detector switches modes in under 1 ms, supporting fast passenger throughput. Wide 2.5-3.6 V supply lets the IC ride bus battery rails with simple LDO. The exposed-pad HVQFN-32 dissipates heat during continuous RF transmission in gated turnstiles.
推荐
Industrial RFID Reader (ISO 15693)
The PN5120A0's native ISO 15693 vicinity-card support and high RF output power make it well-suited for industrial tag readers tracking parts on assembly lines, warehouses, and tool cribs. The integrated data mode detector reads mixed tag populations without host intervention. Host interface flexibility (I2C/SPI/UART) eases integration with PLCs and industrial gateways. The exposed-pad package conducts heat away during continuous RF polling in conveyor applications.
推荐
NFC Peer-to-Pairing & IoT Provisioning
The PN5120A0HN1 supports NFCIP-1 peer-to-peer mode, enabling out-of-band pairing and Wi-Fi/Bluetooth credential hand-off for IoT devices. Its compact HVQFN-32 package fits set-top boxes, smart appliances, and wireless speakers. The integrated data mode detector recognizes NFC Forum tag types (Type 1/2/3/4) without firmware overhead. Low power characteristics suit battery-powered provisioning kiosks; UART host interface provides simple AT-command control.
推荐
eMetering & Wireless Sensor Networks
The PN5120A0HN1 fits utility metering readers (gas, water, electric) where handheld or fixed readers interrogate ISO 14443/15693 tokens on meters. Low 3.3 V operation suits battery-powered tools. The integrated data mode detector reduces host wakeups by allowing command frames to be processed autonomously. The HVQFN-32 package has wide third-party library support including NXP's NFC Reader Library. Compact size suits meter-side modules with restricted board area.
推荐
Printer & Consumable Authentication
NFC authentication in printers, copiers, and 3D printers uses PN5120A0 to verify ink/toner/resin cartridge authenticity with cryptographic MIFARE DESFire tags. The IC's integrated data mode detector and high sensitivity enable one-touch cartridge pairing at the printhead. Wide supply range suits 24 V printer rails after LDO. Compact HVQFN-32 fits on the printhead cable flex with antenna traces printed directly on PET.
推荐
推荐产品汇总
工程参考数据： PN5120A0HN1-C2118 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | PN5120A0HN1/C2,151 | PN5120A0HN1/C2,125 | PN5120A0ET/C2,118 | CLRC66303HN,151 | MFRC63002HN,151 | MFRC52202HN1,118 |
|---|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | HVQFN-32 | HVQFN-32 - same | HVQFN-32 - same | HVQFN-32 - same | HVQFN-32 - same | HVQFN-32 - same | HVQFN-32 - same |
| Carrier Frequency | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz |
| Supply Voltage Range | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 5.5 V (wider) | 2.5 V to 5.5 V (wider) | 2.5 V to 3.6 V |
| Supported Protocols | FeliCa/ISO 14443/ISO 15693/MIFARE/NFCIP-1 | FeliCa/ISO 14443/ISO 15693/MIFARE/NFCIP-1 | FeliCa/ISO 14443/ISO 15693/MIFARE/NFCIP-1 | FeliCa/ISO 14443/ISO 15693/MIFARE/NFCIP-1 | ISO 14443/ISO 15693/MIFARE/NFCIP-1 (no FeliCa) | ISO 14443/MIFARE (no ISO 15693/NFCIP-1) | ISO 14443/MIFARE Classic only |
| Host Interface | I2C/SPI/UART | I2C/SPI/UART | I2C/SPI/UART | I2C/SPI/UART | I2C/SPI/UART | I2C/SPI/UART | I2C/SPI/UART |
| Data Mode Detector | Integrated | Integrated | Integrated | Integrated | Integrated | Integrated | Partial |
| Unit Price (qty 1, USD) | 4.92 | 4.92 | 4.92 | 5.20 | 5.85 | 4.50 | 3.10 |
关键差异点
- Full multi-protocol support including FeliCa （对比 CLRC66303HN,151)
- Lowest cost variant for ISO 14443 only designs （对比 MFRC52202HN1,118)
- Pin-compatible upgrade path to MFRC63002 with wider supply range （对比 MFRC63002HN,151)
设计说明
Per NXP PN5120 datasheet, the antenna loop must be designed for 50 ohm impedance matching, with EMC filter components (typically pi-network) placed within 5 mm of ANT1/ANT2 pads. The exposed thermal pad MUST be soldered to a contiguous PCB ground pour with at least 4 thermal vias to the inner layer for heat dissipation; failure to thermal-via the EPAD may degrade RF performance and cause thermal shutdown during continuous polling. Keep the antenna loop area outside any noisy digital switcher footprint.
Place a 100 nF decoupling capacitor as close as possible to VCC (pin 4) and a 10 uF bulk capacitor within 10 mm. Per the datasheet, the SVDD and AVDD pins each require an additional 100 nF decoupling cap; using the internal regulated outputs without proper bypassing causes high receiver sensitivity loss and ISO 14443 frame error rate above the EMVCo spec.
Pin straps IFSEL0/IFSEL1 must be hard-tied to GND or VCC at PCB level to select I2C, SPI, or UART mode; leaving these floating results in undefined interface mode at boot. The 27.12 MHz crystal oscillator load capacitor selection is critical - NXP recommends 27 pF NPO/C0G ceramic caps trimmed to within 1 pF for ppm-level frequency accuracy required by ISO 14443-3 frame timing.
合规信息
RoHS compliant per NXP product page. Not AEC-Q100 qualified - PN5120 family is for industrial/consumer NFC reader applications, not automotive. Halogen-free reflow-rated per JEDEC J-STD-020 (peak 260 C, MSL-3).
