PXE1110CDMG003XTMA1 - Intel VR12.5/VR13 Digital Controller | Infineon
料号： PXE1110CDMG003XTMA1 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $5.85 | $5.85 |
| 10 | $5.27 | $52.70 |
| 100 | $4.68 | $468.00 |
| 500 | $4.21 | $2,105.00 |
| 1,000 | $3.75 | $3,750.00 |
| 3,000 | $3.3 | $9,900.00 |
PXE1110CDMG003XTMA1 概述
A digital multiphase VR controller is a power management integrated circuit (PMIC) that uses firmware-driven state machines and loop compensation to regulate multiphase synchronous buck converter outputs for microprocessors. The hierarchy flows from multiphase VR controller -> DC-DC controller -> power management IC -> semiconductor. Digital controllers replace analog PWM loops with on-chip DSP-based control, enabling per-rail telemetry, adaptive voltage positioning, and Intel-defined VR12.5/VR13 power-state protocols for Xeon and Core-class CPUs.
Key differentiating features of the PXE1110CDMG003XTMA1 include its 1+1 dual-loop digital architecture, native Intel VR12.5/VR13 SVID protocol support, integrated PMBus 1.2 telemetry, on-chip non-volatile configuration memory, programmable load-line and dynamic VID slew rates, and 6 integrated MOSFET drivers supporting two independent rails. The controller is part of the Primarion family acquired by Infineon and targets compact, high-efficiency server/workstation motherboards.
The PXE1110CDMG003XTMA1 is engineered to drive two independent voltage rails (1+1 phase configuration), with each rail capable of multi-phase expansion via external gate drivers and DrMOS power stages. Internal loop compensation is firmware-defined, eliminating external RC components and reducing BOM count. The PG-VQFN-40-13 package exposes a thermal pad that must be soldered to a top-layer copper pour for stable operation under sustained load.
Typical applications include Intel VR12.5/VR13 server and workstation CPU core voltage rails, dual-rail point-of-load converters for Haswell/Broadwell/Skylake-SP-era platforms, enterprise motherboard CPU socket power, and high-performance computing nodes where digital telemetry, adaptive voltage positioning, and PMBus monitoring are required. Designers pair the controller with Infineon (formerly International Rectifier) DrMOS stages such as the TDA215xx family.
When designing with this part, follow Infineon's reference layout guide: solder the exposed pad to a minimum 1 square-inch copper pour, place the 3.3V decoupling capacitors within 2 mm of the PVCC/VDD pins, and route the SVID/PMBus traces away from switching-node copper to avoid coupling. Designers must also follow the matching external DrMOS datasheet for the gate-drive timing parameters, which are tuned per silicon revision.
This page synthesizes distributor pricing, package diagrams, and drop-in alternatives not found on a single manufacturer datasheet - including the Infineon internal part-numbering breakdown so engineers can confirm that PXE1110CDM-G003 is the bare die variant while PXE1110CDMG003XTMA1 is the tape-and-reel shipping form.
直接替换替代料： PXE1110CDMG003XTMA1 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
PXE1110CDM-G003
✅ 直接替换📋 参考替代料（不在目录中）
IR35201TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
PXE1110CDMG003XTMA1 最大额定值与电气特性
| Manufacturer | Infineon Technologies (Primarion) |
| Part Number (Bare Die Variant) | PXE1110CDM-G003 |
| Part Number (Shipping Variant) | PXE1110CDMG003XTMA1 |
| 功能 | Digital Dual-Output 1+1 Phase PWM Controller |
| Application Standard | Intel VR12.5 and VR13 CPU SVID |
| 输入电压范围 | 3.0 V to 3.6 V (3.3 V nominal) |
| 输出数量 | 6 (two independent rails) |
| 输出类型 | Step-Down (Buck), programmable |
| 拓扑 | Digital multiphase, 1+1 phase configuration |
| 封装 | PG-VQFN-40-13 (QFN 5x5 mm) with EP |
| 安装类型 | Surface Mount (Tape & Reel) |
| 接口 | PMBus 1.2 / I2C / SVID |
| Configuration Memory | On-chip non-volatile (programmable) |
| RoHS 状态 | Compliant (assumed from Tape & Reel suffix X = lead-free) |
| Product Status | Active |
PXE1110CDMG003XTMA1 pg-vqfn-40-13 (qfn 5x5 mm) with ep 引脚配置指南
PXE1110CDMG003XTMA1（pg-vqfn-40-13 (qfn 5x5 mm) with ep 封装）的引脚配置。 该功率器件具有栅极、漏极和源极端子。对于无极性封装，请参阅制造商数据手册以了解确切的引脚 1 方向和封装尺寸细节。常见应用包括电源设计、电机驱动和负载开关。
暂无详细引脚数据： PXE1110CDMG003XTMA1.
请参阅 数据手册 以查看完整引脚配置。
典型应用
PXE1110CDMG003XTMA1 适用于 7 应用s: Intel VR12.5 Server CPU Core Rail, Intel VR13 Workstation Motherboard Power, Dual-Rail Point-of-Load Converter, Enterprise Server PSU Management Daughter Card, High-Performance Computing Node Power, Telecom Blade Server Voltage Regulation, Edge Computing Appliance CPU Power.
Intel VR12.5 Server CPU Core Rail
The PXE1110CDMG003XTMA1 is purpose-built for Intel VR12.5 SVID-compliant server CPU core voltage rails. Its 1+1 dual-output architecture drives two independent CPU domains - typically Vcore and Vcore_sa - from a single controller, reducing board area versus two discrete controllers. The native PMBus 1.2/SVID telemetry provides the load-line and dynamic VID slewing that Xeon-class CPUs require for power-state transitions between P-states and C-states. Engineers pair it with Infineon TDA21535 DrMOS stages to achieve 90%+ peak efficiency at full load. The PG-VQFN-40-13 footprint exposes a thermal pad that must be soldered to a minimum 1 square-inch copper pour for thermal stability.
推荐
Intel VR13 Workstation Motherboard Power
Workstation motherboards based on Intel VR13 (Skylake-SP/Cascade Lake) CPUs require a controller that meets VR13 SVID timing specifications. The PXE1110CDMG003XTMA1 supports both VR12.5 and VR13 protocols, making it a single BOM for the transition from Haswell/Broadwell to Skylake-SP workstations. Its digital firmware stores per-rail configuration in on-chip non-volatile memory, enabling per-platform tuning without external EEPROMs. The 1+1 phase topology is appropriate for workstation CPU segments (TDP 95W-150W) where extreme phase counts are not required. Pair with PMBus-thermal sensor monitoring for system-level platform telemetry.
推荐
Dual-Rail Point-of-Load Converter
Beyond CPU rails, the PXE1110CDMG003XTMA1's two independent regulated outputs make it suitable as a dual-rail POL for memory and chipset domains. Rail 1 can supply a 1.0V to 1.8V memory voltage while Rail 2 generates a 0.6V to 1.2V PCH core rail. Both rails are independently PMBus-addressable and can be sequenced on/off with millisecond resolution. The digital loop eliminates the external RC compensation network required by analog controllers, reducing BOM count. Designers can re-purpose a CPU-Rail reference design for memory+PCH applications, provided the firmware revision supports the alternate rail voltages.
推荐
Enterprise Server PSU Management Daughter Card
In enterprise server power architectures, the PXE1110CDMG003XTMA1 can be used on a management daughter card that monitors and sequences downstream VR phases. Its PMBus 1.2 interface provides per-rail telemetry - voltage, current, temperature, and power - that the BMC uses for system health monitoring. The 6-output PWM capability allows the controller to act as a centralized timing reference for multiple sibling VR phases. Its small 5x5 mm footprint allows placement adjacent to the CPU socket without crowding power-stage copper. The controller's non-volatile configuration memory also simplifies OEM-specific tuning across server SKUs.
推荐
High-Performance Computing Node Power
HPC compute nodes often integrate dense CPU and accelerator silicon on compact boards with strict power budgets. The PXE1110CDMG003XTMA1's dual-rail digital control allows one controller to handle both the CPU Vcore and an adjacent accelerator Vcore, with PMBus-based dynamic power capping. The on-chip non-volatile memory stores platform-specific VID tables that the BMC loads at boot. The controller's firmware update path over PMBus supports field updates without replacing the board, valuable for HPC deployments where service interruptions are costly. Designers should validate against Infineon's thermal model when stacking multiple controllers on the same board.
推荐
Telecom Blade Server Voltage Regulation
Telecom blade servers in NFV/edge deployments use standardized server building blocks but face tighter power-density constraints. The PXE1110CDMG003XTMA1 fits the Intel VR12.5/VR13 reference design footprint and supports PMBus 1.2 telemetry that telecom system management expects. Its 1+1 phase architecture balances per-rail current capability against thermal density in a 5x5 mm package, fitting between high-current phases on the same PCB. The controller's SVID slew-rate control matches telecom CPU idle profiles, helping reduce idle platform power. Reference Infineon evaluation boards are available for telecom OEM qualification.
推荐
Edge Computing Appliance CPU Power
Edge computing appliances bring server-class compute into space- and thermally-constrained chassis. The PXE1110CDMG003XTMA1 supports Intel Xeon D-class and Atom-class CPUs that use VR12.5/VR13 protocols at lower TDPs (35W-95W). Its 1+1 phase output is sufficient for these lower-current CPUs and avoids the cost of higher-phase-count controllers. PMBus telemetry allows remote platform management across the edge fleet. The exposed thermal pad connects to chassis copper for passive cooling. Firmware-configurable rail voltages enable one board SKU to serve multiple CPU variants, simplifying edge appliance manufacturing.
推荐
推荐产品汇总
工程参考数据： PXE1110CDMG003XTMA1 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | PXE1110CDM-G003 | IR35201TRPBF |
|---|---|---|---|
| Package | PG-VQFN-40-13 (QFN 5x5 mm) | PG-VQFN-40-13 (QFN 5x5 mm) - same | PG-VQFN-40 (QFN) - same package type, verify pinout |
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Input Voltage | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V |
| Output Rails | 2 independent (1+1) | 2 independent (1+1) | 2 independent (3+2 base config) |
| PWM Outputs | 6 | 6 | 10 |
| Intel VR Standard | VR12.5 and VR13 | VR12.5 and VR13 | VR12.5 and VR13 |
| Interface | PMBus 1.2 / I2C / SVID | PMBus 1.2 / I2C / SVID | PMBus 1.2 / I2C / SVID |
| Phase Configuration | 1+1 (firmware scalable) | 1+1 (firmware scalable) | 3+2 (firmware scalable) |
| Lifecycle Status | Active | Active | Active |
关键差异点
- Smallest 1+1 dual-output VR12.5/VR13 controller in Infineon portfolio （对比 IR35201TRPBF)
- Same silicon in two ordering codes （对比 PXE1110CDM-G003)
- Native VR12.5 AND VR13 SVID support （对比 Older IR35xx VR11/VR12 controllers)
设计说明
The PXE1110CDMG003XTMA1 dissipates 0.8W to 1.2W in typical dual-rail active operation. The PG-VQFN-40-13 package has an exposed thermal pad that MUST be soldered to a top-layer copper pour of at least 1 square inch (645 mm^2). Without the thermal pad soldered, junction temperature rises 40-60C above datasheet curves and may trigger internal thermal shutdown at moderate ambient temperatures.
Per Infineon's reference layout guide, place 3.3V PVCC decoupling capacitors (10uF X7R ceramic + 0.1uF X7R) within 2 mm of the PVCC and VDD pins. Route the PMBus/SVID traces on an inner layer away from switching-node copper to avoid capacitive coupling that can corrupt SVID packets. Keep the gate-drive output traces matched in length (within 200 mil) to prevent rail timing skew between PWM outputs.
Do not assume the PXE1110CDMG003XTMA1 and IR35201 are interchangeable - while both are 40-pin PG-VQFN packages and share PMBus firmware concepts, their pinout assignments differ for several PWM and VRHOT pins. Always verify the pin remap before PCB rework. Also note that this controller is a low-side device: the high-current CPU rail is generated by external DrMOS stages, not internally.
合规信息
Lead-free (X suffix) and RoHS compliant per the Infineon ordering-code convention. AEC-Q100 is not applicable since this is a server/desktop PMIC, not an automotive-grade part. Halogen-free status not explicitly stated in the verified web data.
