PXE1110CDMG003XTMA1 - Intel VR12.5/VR13 Digital Controller | Infineon
MPN: PXE1110CDMG003XTMA1 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.85 | $5.85 |
| 10 | $5.27 | $52.70 |
| 100 | $4.68 | $468.00 |
| 500 | $4.21 | $2,105.00 |
| 1,000 | $3.75 | $3,750.00 |
| 3,000 | $3.3 | $9,900.00 |
Drop-in alternatives for PXE1110CDMG003XTMA1 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
PXE1110CDM-G003
β Drop-Inπ Reference alternative (not in catalog)
IR35201TRPBF
β Drop-Inπ Reference alternative (not in catalog)
PXE1110CDMG003XTMA1 Maximum Ratings & Electrical Characteristics
| Manufacturer | Infineon Technologies (Primarion) |
| Part Number (Bare Die Variant) | PXE1110CDM-G003 |
| Part Number (Shipping Variant) | PXE1110CDMG003XTMA1 |
| Function | Digital Dual-Output 1+1 Phase PWM Controller |
| Application Standard | Intel VR12.5 and VR13 CPU SVID |
| Input Voltage Range | 3.0 V to 3.6 V (3.3 V nominal) |
| Number of Outputs | 6 (two independent rails) |
| Output Type | Step-Down (Buck), programmable |
| Topology | Digital multiphase, 1+1 phase configuration |
| Package | PG-VQFN-40-13 (QFN 5x5 mm) with EP |
| Mounting Type | Surface Mount (Tape & Reel) |
| Interface | PMBus 1.2 / I2C / SVID |
| Configuration Memory | On-chip non-volatile (programmable) |
| RoHS Status | Compliant (assumed from Tape & Reel suffix X = lead-free) |
| Product Status | Active |
PXE1110CDMG003XTMA1 pg-vqfn-40-13 (qfn 5x5 mm) with ep Pin Configuration Guide
Complete pinout information for PXE1110CDMG003XTMA1 (pg-vqfn-40-13 (qfn 5x5 mm) with ep package). This power device features gate, drain, and source terminals. For non-polarized packages, refer to the manufacturer datasheet for exact pin 1 orientation and footprint details. Common applications include power supply design, motor driving, and load switching.
No detailed pinout data available for PXE1110CDMG003XTMA1.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
PXE1110CDMG003XTMA1 is suitable for 7 applications: Intel VR12.5 Server CPU Core Rail, Intel VR13 Workstation Motherboard Power, Dual-Rail Point-of-Load Converter, Enterprise Server PSU Management Daughter Card, High-Performance Computing Node Power, Telecom Blade Server Voltage Regulation, Edge Computing Appliance CPU Power.
Intel VR12.5 Server CPU Core Rail
The PXE1110CDMG003XTMA1 is purpose-built for Intel VR12.5 SVID-compliant server CPU core voltage rails. Its 1+1 dual-output architecture drives two independent CPU domains - typically Vcore and Vcore_sa - from a single controller, reducing board area versus two discrete controllers. The native PMBus 1.2/SVID telemetry provides the load-line and dynamic VID slewing that Xeon-class CPUs require for power-state transitions between P-states and C-states. Engineers pair it with Infineon TDA21535 DrMOS stages to achieve 90%+ peak efficiency at full load. The PG-VQFN-40-13 footprint exposes a thermal pad that must be soldered to a minimum 1 square-inch copper pour for thermal stability.
Recommended
Intel VR13 Workstation Motherboard Power
Workstation motherboards based on Intel VR13 (Skylake-SP/Cascade Lake) CPUs require a controller that meets VR13 SVID timing specifications. The PXE1110CDMG003XTMA1 supports both VR12.5 and VR13 protocols, making it a single BOM for the transition from Haswell/Broadwell to Skylake-SP workstations. Its digital firmware stores per-rail configuration in on-chip non-volatile memory, enabling per-platform tuning without external EEPROMs. The 1+1 phase topology is appropriate for workstation CPU segments (TDP 95W-150W) where extreme phase counts are not required. Pair with PMBus-thermal sensor monitoring for system-level platform telemetry.
Recommended
Dual-Rail Point-of-Load Converter
Beyond CPU rails, the PXE1110CDMG003XTMA1's two independent regulated outputs make it suitable as a dual-rail POL for memory and chipset domains. Rail 1 can supply a 1.0V to 1.8V memory voltage while Rail 2 generates a 0.6V to 1.2V PCH core rail. Both rails are independently PMBus-addressable and can be sequenced on/off with millisecond resolution. The digital loop eliminates the external RC compensation network required by analog controllers, reducing BOM count. Designers can re-purpose a CPU-Rail reference design for memory+PCH applications, provided the firmware revision supports the alternate rail voltages.
Recommended
Enterprise Server PSU Management Daughter Card
In enterprise server power architectures, the PXE1110CDMG003XTMA1 can be used on a management daughter card that monitors and sequences downstream VR phases. Its PMBus 1.2 interface provides per-rail telemetry - voltage, current, temperature, and power - that the BMC uses for system health monitoring. The 6-output PWM capability allows the controller to act as a centralized timing reference for multiple sibling VR phases. Its small 5x5 mm footprint allows placement adjacent to the CPU socket without crowding power-stage copper. The controller's non-volatile configuration memory also simplifies OEM-specific tuning across server SKUs.
Recommended
High-Performance Computing Node Power
HPC compute nodes often integrate dense CPU and accelerator silicon on compact boards with strict power budgets. The PXE1110CDMG003XTMA1's dual-rail digital control allows one controller to handle both the CPU Vcore and an adjacent accelerator Vcore, with PMBus-based dynamic power capping. The on-chip non-volatile memory stores platform-specific VID tables that the BMC loads at boot. The controller's firmware update path over PMBus supports field updates without replacing the board, valuable for HPC deployments where service interruptions are costly. Designers should validate against Infineon's thermal model when stacking multiple controllers on the same board.
Recommended
Telecom Blade Server Voltage Regulation
Telecom blade servers in NFV/edge deployments use standardized server building blocks but face tighter power-density constraints. The PXE1110CDMG003XTMA1 fits the Intel VR12.5/VR13 reference design footprint and supports PMBus 1.2 telemetry that telecom system management expects. Its 1+1 phase architecture balances per-rail current capability against thermal density in a 5x5 mm package, fitting between high-current phases on the same PCB. The controller's SVID slew-rate control matches telecom CPU idle profiles, helping reduce idle platform power. Reference Infineon evaluation boards are available for telecom OEM qualification.
Recommended
Edge Computing Appliance CPU Power
Edge computing appliances bring server-class compute into space- and thermally-constrained chassis. The PXE1110CDMG003XTMA1 supports Intel Xeon D-class and Atom-class CPUs that use VR12.5/VR13 protocols at lower TDPs (35W-95W). Its 1+1 phase output is sufficient for these lower-current CPUs and avoids the cost of higher-phase-count controllers. PMBus telemetry allows remote platform management across the edge fleet. The exposed thermal pad connects to chassis copper for passive cooling. Firmware-configurable rail voltages enable one board SKU to serve multiple CPU variants, simplifying edge appliance manufacturing.
Recommended
Recommended Products Summary
Engineering reference data for PXE1110CDMG003XTMA1 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PXE1110CDM-G003 | IR35201TRPBF |
|---|---|---|---|
| Package | PG-VQFN-40-13 (QFN 5x5 mm) | PG-VQFN-40-13 (QFN 5x5 mm) - same | PG-VQFN-40 (QFN) - same package type, verify pinout |
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Input Voltage | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V |
| Output Rails | 2 independent (1+1) | 2 independent (1+1) | 2 independent (3+2 base config) |
| PWM Outputs | 6 | 6 | 10 |
| Intel VR Standard | VR12.5 and VR13 | VR12.5 and VR13 | VR12.5 and VR13 |
| Interface | PMBus 1.2 / I2C / SVID | PMBus 1.2 / I2C / SVID | PMBus 1.2 / I2C / SVID |
| Phase Configuration | 1+1 (firmware scalable) | 1+1 (firmware scalable) | 3+2 (firmware scalable) |
| Lifecycle Status | Active | Active | Active |
Key Differentiators
- Smallest 1+1 dual-output VR12.5/VR13 controller in Infineon portfolio (vs IR35201TRPBF)
- Same silicon in two ordering codes (vs PXE1110CDM-G003)
- Native VR12.5 AND VR13 SVID support (vs Older IR35xx VR11/VR12 controllers)
Design Notes
The PXE1110CDMG003XTMA1 dissipates 0.8W to 1.2W in typical dual-rail active operation. The PG-VQFN-40-13 package has an exposed thermal pad that MUST be soldered to a top-layer copper pour of at least 1 square inch (645 mm^2). Without the thermal pad soldered, junction temperature rises 40-60C above datasheet curves and may trigger internal thermal shutdown at moderate ambient temperatures.
Per Infineon's reference layout guide, place 3.3V PVCC decoupling capacitors (10uF X7R ceramic + 0.1uF X7R) within 2 mm of the PVCC and VDD pins. Route the PMBus/SVID traces on an inner layer away from switching-node copper to avoid capacitive coupling that can corrupt SVID packets. Keep the gate-drive output traces matched in length (within 200 mil) to prevent rail timing skew between PWM outputs.
Do not assume the PXE1110CDMG003XTMA1 and IR35201 are interchangeable - while both are 40-pin PG-VQFN packages and share PMBus firmware concepts, their pinout assignments differ for several PWM and VRHOT pins. Always verify the pin remap before PCB rework. Also note that this controller is a low-side device: the high-current CPU rail is generated by external DrMOS stages, not internally.
Compliance Information
Lead-free (X suffix) and RoHS compliant per the Infineon ordering-code convention. AEC-Q100 is not applicable since this is a server/desktop PMIC, not an automotive-grade part. Halogen-free status not explicitly stated in the verified web data.
