SI52208-A02AGMR - 8-Output PCIe Gen 1-4 Clock Generator | Skyworks
料号： SI52208-A02AGMR ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $6.45 | $6.45 |
| 10 | $5.8 | $58.00 |
| 100 | $5.18 | $518.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.12 | $4,120.00 |
SI52208-A02AGMR 概述
A PCI Express clock generator is a dedicated timing IC that synthesizes the low-jitter reference clocks required by PCIe root complexes, endpoints, switches, and retimers. It belongs to the broader category of clock generators and timing ICs within the timing-and-signal-conditioning block of a computing platform, and is typically placed adjacent to the PCIe PHY or switch to minimize trace-induced jitter.
Key features include a 1.5 V to 1.8 V supply range, low power consumption, hardware pin and I2C programmability for output enable and spread spectrum, and integrated 85 ohm source termination that eliminates external resistors on each differential output pair. Compliance with PCIe Gen 1/2/3/4 phase jitter and SRIS reference-clock architectures allows direct deployment in SRNS and SRIS systems without additional PLL stages.
Typical applications include desktop and server PCIe slot clocking, NVMe SSD controllers, PCIe switch reference-clock trees, riser cards, and embedded-computing PCIe endpoints. The wide frequency support (100/133/200 MHz) covers Gen 1/2 (100 MHz) and Gen 3/4 (100 MHz with optional spread) plus a 25 MHz LVCMOS reference path for downstream clocking.
When designing with this device, follow Skyworks reference-layout guidance for the 48-QFN exposed pad to achieve the published jitter and supply-noise performance. Decouple VDD with 0.1 microfarad plus bulk ceramic caps placed within 2 mm of the pins, and route differential pairs to maintain 100 ohm differential impedance with matched length within 5 mils.
This page synthesizes distributor stock, drop-in Skyworks and Silicon Labs family alternatives, and PCIe-specific design notes that complement the manufacturer datasheet.
直接替换替代料： SI52208-A02AGMR ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： SI52208-A02AGMR （相同外形与封装尺寸） ——差异在于 Control Interface, Operating Temperature, Output Type, PCIe Compliance, Package.
快速对比工具——选择替代料号进行并排对比：
SI52208-A01AGM
✅ 直接替换✓ 有现货
$4.1 / 个
查看数据手册 →SI52212-A01AGM
✅ 直接替换📋 参考替代料（不在目录中）
SI52204-A02AGM
✅ 直接替换📋 参考替代料（不在目录中）
SI52202-A02AGM
✅ 直接替换📋 参考替代料（不在目录中）
SI52208-A02AGMR 规格参数
| 功能 | PCIe Gen 1/2/3/4 clock generator |
| 输出数量 | 8 differential HCSL outputs |
| Output Frequencies | 100 MHz / 133 MHz / 200 MHz (selectable) |
| Reference Input | 25 MHz LVCMOS |
| 输出类型 | Differential HCSL with integrated 85 ohm termination |
| 电源电压 | 1.5 V to 1.8 V |
| PCIe Compliance | Gen 1 / Gen 2 / Gen 3 / Gen 4 + SRIS |
| Control Interface | Hardware pins and I2C |
| Spread Spectrum | Hardware and I2C enable/disable |
| Individual Output Enable | Yes (one pin per output) |
| 封装 | 48-pin QFN (6 x 6 mm) with exposed pad |
| 安装类型 | Surface Mount |
| 工作温度 | -40 C to +85 C (industrial) |
| RoHS 状态 | Compliant |
SI52208-A02AGMR 引脚配置
| 引脚 1 | VDD — Core supply, 1.5-1.8 V |
| 引脚 2 | GND — Ground |
| 引脚 3 | XIN/REF — 25 MHz LVCMOS reference input |
| 引脚 4 | XOUT — Reference output (crystal mode) |
| 引脚 5 | SDA — I2C data |
| 引脚 6 | SCL — I2C clock |
| 引脚 7 | OE0 — Output 0 enable, active high |
| 引脚 8 | OE1 — Output 1 enable, active high |
| 引脚 9 | OE2 — Output 2 enable, active high |
| 引脚 10 | OE3 — Output 3 enable, active high |
| 引脚 11 | OE4 — Output 4 enable, active high |
| 引脚 12 | OE5 — Output 5 enable, active high |
| 引脚 13 | OE6 — Output 6 enable, active high |
| 引脚 14 | OE7 — Output 7 enable, active high |
| 引脚 15 | F_SEL0 — Frequency select 0 |
| 引脚 16 | F_SEL1 — Frequency select 1 |
| 引脚 17 | SS_EN — Spread-spectrum enable |
| 引脚 18 | SRIS_EN — SRIS mode enable |
| 引脚 19 | OUT0_P — Differential output 0 positive (HCSL) |
| 引脚 20 | OUT0_N — Differential output 0 negative (HCSL) |
| 引脚 21 | OUT1_P — Differential output 1 positive |
| 引脚 22 | OUT1_N — Differential output 1 negative |
| 引脚 23 | VDD — Output supply |
| 引脚 24 | GND — Ground |
| 引脚 25 | OUT2_P — Differential output 2 positive |
| 引脚 26 | OUT2_N — Differential output 2 negative |
| 引脚 27 | OUT3_P — Differential output 3 positive |
| 引脚 28 | OUT3_N — Differential output 3 negative |
| 引脚 29 | OUT4_P — Differential output 4 positive |
| 引脚 30 | OUT4_N — Differential output 4 negative |
| 引脚 31 | OUT5_P — Differential output 5 positive |
| 引脚 32 | OUT5_N — Differential output 5 negative |
| 引脚 33 | VDD — Output supply |
| 引脚 34 | GND — Ground |
| 引脚 35 | OUT6_P — Differential output 6 positive |
| 引脚 36 | OUT6_N — Differential output 6 negative |
| 引脚 37 | OUT7_P — Differential output 7 positive |
| 引脚 38 | OUT7_N — Differential output 7 negative |
| 引脚 39 | VDD — Output supply |
| 引脚 40 | GND — Ground |
| 引脚 41 | NC — Not connected (per datasheet) |
| 引脚 42 | NC — Not connected (per datasheet) |
| 引脚 43 | NC — Not connected (per datasheet) |
| 引脚 44 | NC — Not connected (per datasheet) |
| 引脚 45 | NC — Not connected (per datasheet) |
| 引脚 46 | NC — Not connected (per datasheet) |
| 引脚 47 | NC — Not connected (per datasheet) |
| 引脚 48 | NC — Not connected (per datasheet) |
典型应用
SI52208-A02AGMR 适用于 6 应用s: Desktop and Workstation PCIe Slot Clocking, Server PCIe Reference-Clock Tree, NVMe SSD Controller Reference Clock, PCIe Switch Fanout, Embedded Computing PCIe Endpoints, Riser Card and Add-In Card Clocking.
Desktop and Workstation PCIe Slot Clocking
The SI52208-A02AGMR delivers eight 100 MHz HCSL clocks from one 48-QFN device, directly driving the PCIe reference-clock pins of root-complex chipsets and downstream slots. Its 4.0 ps RMS phase jitter at Gen 4 holds margin against the PCIe Gen 4 jitter budget of 1.5 ps RMS, and the integrated 85 ohm source termination removes external series resistors for cleaner SI on riser cards.
推荐
Server PCIe Reference-Clock Tree
In 1U/2U servers, the SI52208-A02AGMR's eight outputs feed CPU PCIe lanes, BMC, and riser slots from a single timing IC. Hardware output-enable pins and I2C control support per-slot power-down during low-power states, and the 1.5-1.8 V supply matches the platform's standby rail, avoiding an extra LDO. SRIS support enables modern CPU architectures with separate reference clock domains.
推荐
NVMe SSD Controller Reference Clock
NVMe Gen 3 and Gen 4 SSDs need a clean 100 MHz HCSL reference with tight additive jitter to keep the PCIe eye open over long M.2 traces. The SI52208-A02AGMR provides that with sub-1 ps RMS additive jitter per the Si522xx datasheet, and its small 6x6 mm QFN footprint fits M.2 2230/2280 SSD board layouts. A single 25 MHz crystal feeds the reference input, minimizing BOM cost.
推荐
PCIe Switch Fanout
A PCIe switch such as the PI7C9X111 requires multiple 100 MHz reference clocks to feed its downstream ports. The SI52208-A02AGMR can source all eight downstream HCSL pairs from one IC, simplifying the clock tree and reducing BOM. Hardware OE pins allow unused ports to be disabled for power savings when ports are not populated.
推荐
Embedded Computing PCIe Endpoints
Industrial single-board computers and COM-HPC modules often expose multiple PCIe lanes for GPUs, FPGAs, or NICs. The SI52208-A02AGMR's industrial temperature range (-40 to +85 C) and Gen 4 jitter compliance make it a robust reference-clock source for these systems. Spread-spectrum capability reduces EMI for CE/FCC compliance in compact enclosures.
推荐
Riser Card and Add-In Card Clocking
Add-in cards such as NICs, RAID controllers, and GPUs often need a PCIe reference clock when operating in non-transparent or dual-root configurations. The SI52208-A02AGMR's small footprint and integrated 85 ohm termination simplify the BOM on a constrained PCB, while hardware OE pins let the host turn off the add-in card's clock in standby. The 1.5-1.8 V supply matches auxiliary rails on most add-in cards.
推荐
推荐产品汇总
工程参考数据： SI52208-A02AGMR ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | SI52208-A01AGM | SI52212-A01AGM | SI52204-A02AGM | SI52202-A02AGM |
|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 48-QFN (6x6 mm) | 48-QFN (6x6 mm) - same | 48-QFN (6x6 mm) - same | 48-QFN (6x6 mm) - same | 48-QFN (6x6 mm) - same |
| Number of Outputs | 8 | 8 | 12 (+50%) | 4 (-50%) | 2 (-75%) |
| PCIe Generation | Gen 1/2/3/4 + SRIS | Gen 1/2/3 | Gen 1/2/3 | Gen 1/2/3/4 + SRIS | Gen 1/2/3/4 + SRIS |
| Output Frequencies | 100/133/200 MHz | 100/133/200 MHz | 100/133/200 MHz | 100/133/200 MHz | 100/133/200 MHz |
| Supply Voltage | 1.5-1.8 V | 1.5-1.8 V | 1.5-1.8 V | 1.5-1.8 V | 1.5-1.8 V |
| Reference Input | 25 MHz LVCMOS | 25 MHz LVCMOS | 25 MHz LVCMOS | 25 MHz LVCMOS | 25 MHz LVCMOS |
| Individual Output Enable | Yes | Yes | Yes | Yes | Yes |
| Control Interface | Hardware pins + I2C | Hardware pins + I2C | Hardware pins + I2C | Hardware pins + I2C | Hardware pins + I2C |
关键差异点
- Integrated 85 ohm source termination eliminates external HCSL resistors （对比 Discrete HCSL clock generators without integrated termination)
- PCIe Gen 4 + SRIS compliance in the same 48-QFN family （对比 A01 order code in same family)
- 8 outputs from a single 6x6 mm QFN （对比 SI52204-A02AGM with 4 outputs)
设计说明
Place the SI52208-A02AGMR as close as possible to the PCIe root-complex or switch reference-clock input pins to minimize trace-induced jitter. Each HCSL differential pair should be routed as 100 ohm differential with intra-pair length matching within 5 mils. The exposed pad must be soldered to a continuous ground plane with thermal vias for heat dissipation and return-current continuity.
Decouple each VDD pin with a 0.1 microfarat X7R ceramic capacitor placed within 2 mm of the pin, plus a 1 microfarad bulk capacitor. The SI52208-A02AGMR is sensitive to supply noise on the 1.5-1.8 V rail; for low-jitter PCIe Gen 3/4 operation, derive this rail from a low-noise LDO rather than the main switching converter output.
Do not enable spread spectrum simultaneously on both upstream and downstream devices, as cascaded spread can exceed the PCIe jitter budget. Verify the F_SEL0/F_SEL1 pins match the platform's required frequency at every power-up, since I2C register changes can be lost if the optional non-volatile memory is not used. Refer to the Skyworks Si522xx datasheet register map section for OE pin polarity and SRIS_EN behavior at startup.
合规信息
RoHS and REACH compliance per Skyworks product page. Not AEC-Q100 qualified - this part targets commercial/industrial PCIe platforms, not automotive. Halogen-free status not stated in available data and set to 'unknown'.
