SI5335B-B01461-GM - 4-Output Any-Freq Clock Generator | Skyworks
料号： SI5335B-B01461-GM ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.05 | $130.50 |
| 100 | $11.32 | $1,132.00 |
| 500 | $10.18 | $5,090.00 |
| 1,000 | $9.05 | $9,050.00 |
SI5335B-B01461-GM 概述
A clock generator is a semiconductor device that produces one or more precise timing references from a single input frequency source, replacing multiple discrete oscillators to reduce BOM cost and board area. The Si5335B family belongs to the broader category of clock generators, frequency synthesizers, and phase-locked loops (PLLs) used in any electronic system that requires synchronized timing. By integrating a PLL with a fractional-N MultiSynth divider, the Si5335B can derive multiple unrelated output frequencies from a single low-cost external crystal, an architectural choice that simplifies supply chains versus stocking four discrete XOs.
The Si5335B-B01461-GM provides four output banks, each of which can be configured as one differential pair or two single-ended CMOS clocks. Its core MultiSynth technology independently synthesizes each output, eliminating phase alignment between banks. Integrated configurable output drivers support LVDS, LVPECL, HCSL, CML, and CMOS swing levels, removing the need for external translator ICs. An I2C/SPI interface allows in-system reconfiguration of frequency and format. Power is drawn from a single 1.8V to 3.3V supply, and the device operates over the industrial -40C to +85C temperature range.
Typical applications include general-purpose clock tree replacement, networking and telecom line cards, multi-processor and FPGA/ASIC reference clocks, test and measurement equipment, and PCIe timing fan-out. The compact 4x4 mm QFN footprint and high integration make the Si5335B-B01461-GM especially attractive in dense PCB designs where multiple clock sources would otherwise compete for board area.
When designing with this part, use the free ClockBuilder Pro software to generate the exact frequency plan and register configuration for your project. Place the external 8-32 MHz crystal or reference input as close to the XIN/XOUT pins as possible to minimize jitter, and provide a solid ground plane under the exposed pad (EP) for thermal dissipation and return-path integrity.
直接替换替代料： SI5335B-B01461-GM ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
SI5335B-B01461-GMR
✅ 直接替换📋 参考替代料（不在目录中）
SI5335B-B11355-GM
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
SI5335B-B11535-GM
✅ 直接替换📋 参考替代料（不在目录中）
SI5335B-B11461-GM
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
SI5335A-B01461-GM
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
SI5335B-B01461-GM 规格参数
| 功能 | 4-output any-frequency any-output clock generator |
| 输出数量 | 4 banks (1 differential or 2 single-ended per bank) |
| Output Frequency Range | 1 MHz to 200 MHz (per output) |
| Input Reference | External crystal 8-32 MHz or single-ended clock |
| 电源电压 | 1.8 V to 3.3 V |
| Output Types Supported | LVDS, LVPECL, HCSL, CML, CMOS |
| Programming Interface | I2C / SPI |
| 封装 | 24-pin QFN-EP (4x4 mm) |
| 工作温度 | -40 C to +85 C |
| 引脚数 | 24 |
| 安装类型 | Surface Mount |
| Synthesis Architecture | MultiSynth fractional-N per output |
| Configuration Method | Custom factory programmed (B0xxxx ordering code) + ClockBuilder Pro |
| RoHS 状态 | Compliant |
| 分类 | Clock Generator / PLL / Frequency Synthesizer |
SI5335B-B01461-GM 引脚配置
| 引脚 1 | SDA/SDIO — I2C data / SPI I/O |
| 引脚 2 | SCL/SCLK — I2C clock / SPI clock |
| 引脚 3 | A1 — I2C address select |
| 引脚 4 | A0 — I2C address select |
| 引脚 5 | GND — Ground |
| 引脚 6 | VDD — Core supply (1.8V-3.3V) |
| 引脚 7 | XIN — Crystal input / external reference input |
| 引脚 8 | XOUT — Crystal output (leave NC if external reference used) |
| 引脚 9 | VDDO0 — Output bank 0 supply (1.8V-3.3V) |
| 引脚 10 | OUT0A+ — Output 0A positive |
| 引脚 11 | OUT0A- — Output 0A negative |
| 引脚 12 | OUT0B+ — Output 0B positive (or CMOS0B if configured single-ended) |
| 引脚 13 | OUT0B- — Output 0B negative |
| 引脚 14 | VDDO1 — Output bank 1 supply |
| 引脚 15 | OUT1A+ — Output 1A positive |
| 引脚 16 | OUT1A- — Output 1A negative |
| 引脚 17 | OUT1B+ — Output 1B positive |
| 引脚 18 | OUT1B- — Output 1B negative |
| 引脚 19 | VDDO2 — Output bank 2 supply |
| 引脚 20 | OUT2A+ — Output 2A positive |
| 引脚 21 | OUT2A- — Output 2A negative |
| 引脚 22 | OUT2B+ — Output 2B positive |
| 引脚 23 | OUT2B- — Output 2B negative |
| 引脚 24 | EP — Exposed pad - connect to GND for thermal dissipation |
典型应用
SI5335B-B01461-GM 适用于 6 应用s: General-Purpose Clock Tree Replacement, Networking & Telecom Line Cards, FPGA / ASIC Multi-Clock Reference, Industrial Test & Measurement, PCIe Gen 2/3 Reference Clock Fan-Out, Solid-State Storage & SSD Controller Boards.
General-Purpose Clock Tree Replacement
The SI5335B-B01461-GM replaces up to four discrete XOs with a single factory-programmed device, cutting board area and BOM cost in multi-clock designs. With four independent any-frequency outputs from 1 MHz to 200 MHz, it eliminates phase-alignment headaches between discrete oscillators. Power consumption at 1.8V to 3.3V is far lower than driving four XOs, and the 24-QFN-EP footprint frees routing space for high-density PCBs.
推荐
Networking & Telecom Line Cards
The SI5335B-B01461-GM supplies independent reference clocks to Ethernet PHYs, switch ASICs, and timing ICs in line cards, each running at unrelated frequencies (e.g. 156.25 MHz, 125 MHz, 100 MHz, 50 MHz). LVDS/LVPECL/HCSL output formats let it drive PHYs and ASICs natively without level translators. The 1.8V to 3.3V supply matches typical line-card rails, and industrial -40C to +85C operation tolerates outdoor enclosures and central office environments.
推荐
FPGA / ASIC Multi-Clock Reference
The SI5335B-B01461-GM drives FPGAs and ASICs that need multiple unrelated reference clocks (e.g. system, fabric, transceivers, memory controller) from one source. Each bank drives one differential pair or two single-ended CMOS clocks, mapped 1:1 to common FPGA clock pin pairs. The integrated PLL and MultiSynth fractional-N synthesis avoid jitter spurs from cascaded dividers, and ClockBuilder Pro generates the exact register map for any frequency combination required.
推荐
Industrial Test & Measurement
The SI5335B-B01461-GM delivers low-jitter, stable reference clocks for oscilloscopes, protocol analyzers, and ATE, where 1 ppm frequency accuracy is critical. With per-bank programmable output format and frequency, a single SI5335B can drive multiple ADC front-ends and serializer clocks that need unrelated sample rates. Wide 1.8V to 3.3V supply lets it share rails with precision data converters; rugged -40C to +85C operation covers factory-floor temperature ranges.
推荐
PCIe Gen 2/3 Reference Clock Fan-Out
The SI5335B-B01461-GM distributes 100 MHz PCIe reference clocks to multiple endpoints from one source, eliminating per-endpoint discrete oscillators. HCSL output format matches PCIe electrical specs directly without external termination, and sub-100 ps rms jitter is well within PCIe Gen 3 jitter budgets. The factory-programmed B-code approach means no in-system programming is required for compact PCIe expansion cards, saving firmware development overhead.
推荐
Solid-State Storage & SSD Controller Boards
The SI5335B-B01461-GM supplies reference clocks to enterprise SSD controllers, NAND flash PHY, and DRAM interfaces, each requiring tight-jitter, unrelated frequency references. Its compact 24-QFN-EP package saves critical board area in stacked-edge SSDs where height profiles are constrained, and CMOS output swing directly drives controller PLL reference inputs with no level translation. Industrial temperature rating supports JEDEC enterprise SSD thermal envelopes and demanding NVMe-OF deployments.
推荐
推荐产品汇总
工程参考数据： SI5335B-B01461-GM ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | SI5335B-B01461-GMR | SI5335B-B11355-GM | SI5335B-B11535-GM | SI5335A-B01461-GM |
|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions (same) | Skyworks Solutions (same) | Skyworks Solutions (same) | Skyworks Solutions (same) |
| Package | 24-QFN-EP (4x4 mm) | 24-QFN-EP (4x4 mm) - same | 24-QFN-EP (4x4 mm) - same | 24-QFN-EP (4x4 mm) - same | 24-QFN-EP (4x4 mm) - same |
| Output Count | 4 banks | 4 banks | 4 banks | 4 banks | 4 banks |
| Output Frequency Range | 1-200 MHz | 1-200 MHz | 1-200 MHz | 1-200 MHz | 1-200 MHz |
| Frequency Plan (B-code) | B01461 | B01461 (identical) | B11355 (different) | B11535 (different) | B01461 (identical but A-suffix driver profile) |
| Supply Voltage | 1.8V to 3.3V | 1.8V to 3.3V | 1.8V to 3.3V | 1.8V to 3.3V | 1.8V to 3.3V |
| Output Formats | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS (different default driver profile) |
| Packaging Media | Tray (GM) | Tape & Reel (GMR) | Tray (GM) | Tray (GM) | Tray (GM) |
关键差异点
- Factory-customizable frequency plan via B-code ordering （对比 Generic clock generators (e.g. CDCE906, CDCM61002))
- Independently synthesized 4 non-integer-related outputs （对比 Si5338 or cascaded PLLs)
- Multi-format differential outputs without level translators （对比 Si52208 or 9LPRS491)
设计说明
Place the external 8-32 MHz crystal or single-ended reference clock within 5 mm of pins 7 (XIN) and 8 (XOUT). Use a guard ring tied to GND around the crystal traces to suppress coupled noise and keep the entire PLL loop in compliance with the datasheet's input reference sensitivity. Decouple VDD (pin 6) and each VDDOx (banks 0/1/2) with a 0.1 uF X7R ceramic cap within 2 mm of the pin and a 10 uF bulk cap on the same rail. Connect the exposed pad (EP, pin 24) to a 4 mm x 4 mm GND copper pour with at least 4 thermal vias to the inner GND plane for thermal dissipation and return-path integrity.
Do not leave unused output banks floating - tie unused OUTx+/OUTx- to GND via a 50-ohm termination to prevent spurious emissions from causing EMI test failures. If using CMOS single-ended output, leave the complementary negative pin either unused or terminated to avoid coupling into adjacent signals. The factory B-code programming defines the initial frequency plan; attempting in-system reprogramming without first verifying ClockBuilder Pro compatibility can brick the I2C/SPI interface into an uninitialized state. Always verify the B-code ordering code matches the desired frequency plan via the Skyworks customer support portal before sending to manufacturing.
Differential outputs (LVDS/LVPECL/HCSL) require 100-ohm differential impedance routing with matched-pair length tuning to within 150 mils to maintain adequate timing margin for high-speed downstream PHYs. Source-series termination (typically 33 ohms) at the Si5335B output helps absorb reflections at the connector or far-end receiver. Estimated: at 200 MHz output with 4 mm (about 150 mil) differential pair mismatch, the timing skew introduced is roughly 7 ps - well within PCIe and GbE jitter budgets but visible to high-end test equipment, so length matching is still required.
合规信息
RoHS compliant and lead-free per JLCPCB listing. Industrial -40C to +85C grade; not AEC-Q100 qualified. Halogen-free status not explicitly disclosed in available product documentation.
