ST10R167-Q3 - 16-Bit 25MHz ROMless MCU | STMicroelectronics
料号： ST10R167-Q3 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $22.1 | $221.00 |
| 100 | $19.6 | $1,960.00 |
| 500 | $17.8 | $8,900.00 |
| 1,000 | $16.4 | $16,400.00 |
ST10R167-Q3 概述
A ROMless microcontroller is a member of the microcontroller (MCU) hierarchy that contains no internal non-volatile program memory; it executes code stored in external EPROM, flash, or EEPROM devices. Within the power-management-of-compute hierarchy, the ST10R167-Q3 sits in the 16-bit embedded microcontroller class, positioned above simple 8-bit MCUs and below 32-bit parts, making it a classic choice for real-time embedded control systems that need external, field-updatable firmware.
Key differentiating features include the 4-stage pipelined 16-bit CPU delivering 12.5 MIPS, enhanced boolean bit-manipulation facilities, additional instructions supporting high-level languages and operating systems, on-chip PLL clock generation from a low-frequency crystal, a high-speed synchronous serial channel (SSC), and the CAN 2.0B module for robust vehicle and industrial networking. According to the STMicroelectronics datasheet, the device operates from a 4.5V to 5.5V supply over a -40C to +125C temperature range (the Q3 suffix grade).
Architecturally, the ST10R167 derives from the proven ST10 (SAB 80C166-derived) family, combining a fast Harvard-style memory structure with a rich peripheral event controller that handles interrupt-driven I/O with minimal CPU overhead. The external bus interface supports multiplexed or demultiplexed modes, letting designers size code memory to the application.
Typical applications include automotive engine management and body electronics, industrial motor control and automation, communication equipment, and instrumentation systems where 16-bit real-time performance plus CAN connectivity are required.
A key design consideration is that the ROMless architecture mandates external program memory: budget bus timing, wait states, and PCB routing for the external bus, and verify that the 4 KB on-chip RAM is sufficient for data and stack in your real-time workload.
This page adds engineering value beyond the manufacturer datasheet by compiling drop-in family alternatives, pricing context, design notes, and application guidance in one structured, machine-readable resource.
直接替换替代料： ST10R167-Q3 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
ST10R167-Q6
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ST10F167
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ST10R163-Q3
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ST10R167-Q3/TR
✅ 直接替换📋 参考替代料（不在目录中）
ST10F269
✅ 直接替换📋 参考替代料（不在目录中）
ST10R167-Q3 最大额定值与电气特性
| Core Processor | ST10 16-bit CPU, 4-stage pipeline |
| Core Size | 16-bit |
| 最大时钟频率 | 25 MHz |
| Instruction Cycle Time | 80 ns at 25 MHz |
| Performance | 12.5 MIPS |
| Program Memory Type | ROMless (external) |
| RAM Size | 4 KB on-chip high-speed RAM |
| Number of I/O | 111 |
| CAN Interface | 1 x CAN 2.0B |
| A/D Converter | 16 x 10-bit |
| Serial Interfaces | SSC (high-speed synchronous serial channel), ASC |
| Oscillator Type | Internal (PLL clock generation) |
| 电源电压 | 4.5 V to 5.5 V |
| 工作温度 | -40C to +125C |
| 封装 / 外壳 | 144-PQFP (28x28 mm) |
| 安装类型 | Surface Mount |
| External Bus Interface | Multiplexed / demultiplexed external memory bus |
ST10R167-Q3 144-pqfp (28x28 mm) 引脚配置指南
ST10R167-Q3（144-pqfp (28x28 mm) 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： ST10R167-Q3.
请参阅 数据手册 以查看完整引脚配置。
典型应用
ST10R167-Q3 适用于 6 应用s: Automotive Engine and Body Control, Industrial Motor Control and Automation, Communication Equipment Controllers, Instrumentation and Test Equipment, Embedded Real-Time Control Systems, Legacy System Maintenance and Repair.
Automotive Engine and Body Control
The ST10R167-Q3 fits automotive electronic control units because the Q3 grade is specified from -40C to +125C and the integrated CAN 2.0B controller connects directly to in-vehicle networks such as powertrain and body buses. The 16-bit CPU executes a 4-stage pipeline at 25 MHz, delivering 12.5 MIPS with an 80 ns instruction cycle, which is sufficient for closed-loop engine timing, valve control, and body-function scheduling. The 16-channel 10-bit ADC digitizes sensor inputs (temperature, pressure, throttle position) without external conversion hardware. In this application the ROMless architecture allows the ECU firmware to live in external flash or EPROM, simplifying variant management across vehicle platforms; the trade-off is extra board area and bus routing for the code memory devices.
推荐
Industrial Motor Control and Automation
For variable-frequency drives, servo controllers, and PLC modules, the ST10R167-Q3 offers the peripheral event controller and enhanced capture/compare timer resources typical of the ST10 family, letting PWM generation and sensor sampling proceed with minimal CPU intervention. The 12.5 MIPS core headroom covers field-oriented control inner loops at moderate switching frequencies, while the 16-channel 10-bit ADC reads current-shunt and position feedback across multiple phases. Its 111 I/O lines interface directly to contactors, encoders, and HMI signals, and the CAN 2.0B port links the drive onto industrial fieldbus segments. Because industrial drives need field-updatable firmware, most implementations place code in external flash via the demultiplexed bus interface; designers should budget wait states so memory access time does not erode the 80 ns instruction-cycle advantage.
推荐
Communication Equipment Controllers
Line-card supervision, protocol conversion nodes, and telecom backplane controllers benefit from the ST10R167-Q3 combination of a synchronous serial channel (SSC) for high-speed slave/master communication with other processors, a general-purpose asynchronous serial channel, and CAN for equipment-level management networks. The SSC's double-buffered transmit/receive with its own 16-bit baud-rate generator offloads serial framing from the CPU, preserving pipeline throughput for protocol stack code held in external memory. The 5V I/O tolerance matches legacy telecom board-level signaling directly, avoiding level-shift stages that a 3.3V modern MCU would require. Systems with high code volumes use the ROMless external bus to map large EPROM/flash images, and the 4 KB on-chip RAM serves as a zero-wait-state stack and variable area for the real-time executive.
推荐
Instrumentation and Test Equipment
Bench instruments, data loggers, and process meters exploit the ST10R167-Q3's 16-channel 10-bit ADC to multiplex many analog sensor channels into one conversion block, while the 12.5 MIPS core performs scaling, linearization, and display formatting in real time. The Q3 automotive temperature rating of -40C to +125C also makes the device acceptable for ruggedized field instruments exposed to outdoor environments. The on-chip PLL generates the 25 MHz system clock from a lower-frequency crystal, easing EMC design in sensitive measurement front ends by allowing slower crystal oscillation. Because instrument firmware typically grows over a product's life, storing code in a socketed external flash on the ROMless bus enables field upgrades without replacing the microcontroller - a key maintenance advantage for installed instrument fleets.
推荐
Embedded Real-Time Control Systems
General real-time embedded systems - from building control panels to vending and gate controllers - use the ST10R167-Q3 where deterministic 16-bit execution, bit-manipulation instructions, and rich interrupt structures matter more than raw processing power. The ST10 instruction set includes enhanced boolean operations that map switch-contact logic and interlock chains directly onto peripheral registers and port bits, and additional instructions supporting high-level languages and operating systems simplify development under a small RTOS. The 111 GPIOs drive keypads, relays, and indicators, while the external bus supports the memory expansion that larger application code requires. Designers should partition time-critical routines into the 4 KB on-chip RAM to exploit zero-wait-state access, keeping the external bus for less timing-sensitive code.
推荐
Legacy System Maintenance and Repair
A substantial installed base of ST10-based controllers in automotive, industrial, and medical equipment still requires board-level repair and low-volume reproduction. For these spares and repair workflows, the ST10R167-Q3 remains procurable through distributors (DigiKey listing showed same-day shipping as of 2026-10-07) and the broker network aggregated by Octopart across 27 distributors. Replacement boards can reuse the original external memory map and firmware images unchanged because the device is drop-in compatible with prior ST10R167 grades in the 144-PQFP footprint. Maintenance engineers should verify date codes and buy buffer stock given end-of-life status, and where stock tightens, the same-package ST10F167/ST10R163 family members provide fallback options after a pinout and timing review against the respective datasheets.
推荐
推荐产品汇总
工程参考数据： ST10R167-Q3 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ST10R167-Q6 | ST10F167 | ST10R163-Q3 | ST10F269 |
|---|---|---|---|---|---|
| Package | 144-PQFP (28x28 mm) | 144-PQFP (28x28 mm) - same | 144-PQFP (28x28 mm) - same | 144-PQFP (28x28 mm) - same | 144-PQFP (28x28 mm) - same |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Program Memory | ROMless (external) | ROMless (external) | — | ROMless (external) | On-chip Flash (larger) |
| CAN Interface | 1 x CAN 2.0B | 1 x CAN 2.0B | 1 x CAN 2.0B | CAN capability per variant | 2 x CAN (per family docs) |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 5 V (4.5 V to 5.5 V) | 5 V (4.5 V to 5.5 V) | 5 V (4.5 V to 5.5 V) |
关键差异点
- External code flexibility with proven 16-bit core （对比 ST10F167)
- Higher performance headroom within the same footprint （对比 ST10R167-Q6)
- Full peripheral set vs reduced variant （对比 ST10R163-Q3)
设计说明
The ROMless external bus dominates the PCB layout of an ST10R167-Q3 system. In demultiplexed mode, latch the multiplexed address with a 74x573-class transparent latch clocked by ALE, and keep the latch within a few centimeters of the MCU to preserve setup/hold margins at 25 MHz. Route the 16-bit data bus as short, direct traces and avoid stubs on address lines. Place a 100 nF ceramic decoupling capacitor at every VDD/VSS pin pair plus one bulk 10 uF per supply domain, and connect the analog ADC supply according to the datasheet reference-design filtering to protect 10-bit conversion accuracy.
Verify external memory speed against the bus controller configuration. At 25 MHz the instruction cycle is 80 ns; with zero wait states the external code memory must be fast enough for the selected bus mode. If using 90 ns or 120 ns flash/EPROM, program the MCTC (memory cycle time) wait-state fields accordingly - a misconfigured wait-state setting is the most common cause of intermittent ST10 failures that appear only at hot temperature or low supply voltage. Also confirm the RESET pin circuit: the datasheet states an internal pull-up permits power-on reset using only a capacitor to VSS, so size it for the required reset duration while the oscillator starts.
The device requires a regulated 5V rail (4.5 V to 5.5 V) across the full -40C to +125C range; in automotive contexts add transient protection (load-dump clamping and reverse polarity handling) upstream of the MCU per STMicroelectronics ST10 application notes. Estimated: total current is the core ICC plus I/O load; with many of the 111 outputs driving LED or optocoupler loads, I/O current can exceed core current, so budget the supply regulator for the sum, not the datasheet ICC alone. Sequence external memory and bus transceivers with the MCU or ensure all 5V devices tolerate simultaneous power-up to avoid bus contention during reset.
合规信息
Compliance data was not present in the verified web data for this legacy EOL part. Check the STMicroelectronics product page or distributor compliance certificates for the specific date code.
