THS1040CPWRG4 - 10-Bit 40 MSPS Low-Power ADC | Texas Instruments
料号： THS1040CPWRG4 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $6.5 | $6.50 |
| 10 | $5.85 | $58.50 |
| 100 | $5.2 | $520.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.1 | $4,100.00 |
THS1040CPWRG4 概述
An ADC is a data-conversion integrated circuit that samples continuous analog signals and quantizes each sample into a discrete digital code. Pipeline ADCs such as the THS1040CPWRG4 use multiple low-resolution stages with inter-stage digital correction to achieve high sampling rates at moderate power consumption. Within the broader taxonomy, this part is a successive-stage pipeline ADC, sits under high-speed ADC, then data converter, then signal chain, then power management/data-conversion IC. Single 3 V supply, 10-bit resolution, and 40 MSPS conversion rate make this ADC a mid-resolution, mid-throughput solution for embedded DSP and FPGA interfaces.
Key features include ±0.45 LSB typical differential nonlinearity (DNL), 60 dB signal-to-noise ratio at 4.8 MHz input, 72 dB spurious-free dynamic range, and configurable input functions. The pipelined architecture with digital error correction delivers low latency relative to sigma-delta converters while drawing milliwatts of power from a single 3 V rail, making the part well-suited for portable and thermally constrained designs.
Architecture depth: the THS1040 family uses a multi-stage switched-capacitor pipeline, an internal bandgap-derived reference, and CMOS input comparators. The configurable reference allows the designer to scale the analog input range between 1 Vp-p and 2 Vp-p full-scale, easing interface to common op-amp output levels and to differential drivers. Internal voltage reference can be set for 1 Vp-p or 2 Vp-p full-scale input. The PW suffix denotes the tape-and-reel TSSOP-28 option, and the G4 suffix denotes a Pb-free green packaging finish compliant with RoHS requirements.
Typical applications include digital still cameras, video capture front-ends, CCD digitizers, ultrasound imaging receivers, set-top box video digitizers, and digital communications IF sampling. Single 3 V supply simplifies power-tree design for battery-powered portable instruments where the ADC sits adjacent to a low-power DSP or FPGA fabric.
Design consideration: place the analog and digital decoupling capacitors as close as possible to the AVDD and DVDD pins respectively, and use a ground plane to isolate the analog input traces from the digital output bus. The internal reference selection bit trades reference stability against full-scale input range, and designers must select the configuration best matching the upstream op-amp drive capability.
This page synthesizes distributor pricing, drop-in same-package and cross-package alternatives, parametric comparison tables, and practical PCB design notes not found in the manufacturer datasheet, all anchored to verified web data as of 2026-10-15.
直接替换替代料： THS1040CPWRG4 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： THS1040CPWRG4 （相同外形与封装尺寸） ——差异在于 Package, RoHS Status, Input Type, Number of Channels, Architecture.
快速对比工具——选择替代料号进行并排对比：
THS1041CPWRG4
✅ 直接替换📋 参考替代料（不在目录中）
THS1040CPWR
✅ 直接替换📋 参考替代料（不在目录中）
THS1040IPWR
✅ 直接替换📋 参考替代料（不在目录中）
THS1031IPWRG4
✅ 直接替换✓ 有现货
$3.42 / 个
查看数据手册 →THS1031IPWG4
✅ 直接替换✓ 有现货
$3.38 / 个
查看数据手册 →THS1040CPWRG4 最大额定值与电气特性
| 分辨率 | 10 bit |
| Number of Channels | 1 Input |
| 采样率 | 40 MSPS |
| Architecture | Pipelined |
| Analog Supply Voltage | 3 V |
| Digital Supply Voltage | 3 V |
| Analog Input Configuration | Single-ended or Differential |
| Differential Nonlinearity (DNL) | ±0.45 LSB (typ) |
| Signal-to-Noise Ratio (SNR) | 60 dB typ at 4.8 MHz |
| Spurious-Free Dynamic Range (SFDR) | 72 dB |
| Internal Voltage Reference | Adjustable, supports 1 Vp-p and 2 Vp-p full-scale |
| Input Range | 1 Vp-p to 2 Vp-p (configurable) |
| 工作温度范围 | 0C to +70C (commercial grade) |
| 封装 | 28-pin TSSOP (PW) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (Pb-free G4 finish) |
| MSL 等级 | 2 (per TI standard) |
THS1040CPWRG4 引脚配置
| 引脚 1 | AVDD — Analog 3 V supply |
| 引脚 2 | AIN+ — Analog input (positive) |
| 引脚 3 | AIN- — Analog input (negative) |
| 引脚 4 | REFT — Top reference decoupling |
| 引脚 5 | REFB — Bottom reference decoupling |
| 引脚 6 | REFCM — Common-mode reference |
| 引脚 7 | REFOUT — Reference output |
| 引脚 8 | REFIN — Reference input |
| 引脚 9 | VREF — Voltage reference select |
| 引脚 10 | PD — Power-down control |
| 引脚 11 | OE — Output enable |
| 引脚 12 | CLK — Clock input |
| 引脚 13 | DVDD — Digital 3 V supply |
| 引脚 14 | DGND — Digital ground |
| 引脚 15 | D9 — Digital output bit 9 (MSB) |
| 引脚 16 | D8 — Digital output bit 8 |
| 引脚 17 | D7 — Digital output bit 7 |
| 引脚 18 | D6 — Digital output bit 6 |
| 引脚 19 | D5 — Digital output bit 5 |
| 引脚 20 | D4 — Digital output bit 4 |
| 引脚 21 | D3 — Digital output bit 3 |
| 引脚 22 | D2 — Digital output bit 2 |
| 引脚 23 | D1 — Digital output bit 1 |
| 引脚 24 | D0 — Digital output bit 0 (LSB) |
| 引脚 25 | NC — Not connected (per datasheet) |
| 引脚 26 | NC — Not connected (per datasheet) |
| 引脚 27 | AGND — Analog ground |
| 引脚 28 | AGND — Analog ground |
典型应用
THS1040CPWRG4 适用于 6 应用s: Digital Still Camera Image Digitizer, CCD Imaging Front-End, Set-Top Box Video Digitizer, Digital Communications IF Sampling, Ultrasound Imaging Receiver, Portable Test and Measurement Instrumentation.
Digital Still Camera Image Digitizer
The THS1040CPWRG4 fits digital still camera image digitization thanks to its 40 MSPS sampling rate, which exceeds typical CCD horizontal line rates of 20-30 MSPS, and its single 3 V supply that simplifies camera power-rail design. The 10-bit resolution matches the dynamic range of consumer CCD imagers, and the 60 dB SNR at 4.8 MHz input preserves image detail in mid-range pixel clock frequencies. Placed between the CCD output amplifier and the image DSP, the ADC digitizes analog pixel streams into 10-bit parallel data using a pixel-rate clock; unlike sigma-delta converters, the pipelined architecture adds only a few clock cycles of latency, which is critical for real-time preview and burst-mode capture pipelines in compact camera designs.
推荐
CCD Imaging Front-End
The THS1040CPWRG4 is well-suited for CCD imaging front-end applications where analog pixel streams must be digitized at rates up to 40 MSPS with 10-bit precision. Its configurable 1 Vp-p or 2 Vp-p full-scale input range matches typical CCD output amplitudes, and the single 3 V supply eases integration into compact imaging modules. The pipelined architecture delivers sub-microsecond conversion latency versus sigma-delta alternatives that would require decimation filters. Used between the CCD analog front-end amplifier and an FPGA or DSP processor, the ADC samples each pixel at the pixel-clock rate and presents the 10-bit digital word on the parallel bus; designers should expect approximately 50 mW power consumption at full 40 MSPS operation from the 3 V supply.
推荐
Set-Top Box Video Digitizer
Set-top box video digitizers benefit from the THS1040CPWRG4's 40 MSPS sampling rate, which exceeds the 27 MHz pixel rate of standard-definition video and provides headroom for higher-resolution video formats. The 10-bit resolution delivers studio-quality video capture with sufficient dynamic range for Y/C separation and color decoding. Single 3 V operation simplifies power-tree design in fanless set-top enclosures with strict thermal budgets. The ADC digitizes the analog video input after anti-alias filtering and presents composite digital video on the 10-bit parallel bus; the pipelined architecture adds only 2-3 clock cycles of latency, which is acceptable for real-time video processing pipelines used in MPEG encoders.
推荐
Digital Communications IF Sampling
IF sampling in digital communications receivers leverages the THS1040CPWRG4's 40 MSPS rate and 60 dB SNR at 4.8 MHz to digitize intermediate-frequency signals from a superheterodyne downconverter. The 72 dB SFDR ensures spurious content from neighboring channels stays below detection thresholds in narrow-band receivers. Single 3 V supply simplifies integration into portable and battery-powered radio designs. The ADC samples the IF signal at 40 MSPS and presents a 10-bit digital stream to a digital downconverter implemented in an FPGA; the pipelined architecture introduces deterministic latency that simplifies digital channelizer synchronization across multiple receiver channels.
推荐
Ultrasound Imaging Receiver
Ultrasound imaging receivers use the THS1040CPWRG4 to digitize analog echo signals at rates up to 40 MSPS with 10-bit resolution, matching the bandwidth of mid-frequency ultrasound probes (5-10 MHz). The single 3 V supply reduces heat dissipation in handheld and cart-based ultrasound systems where patient safety and operator comfort require low component temperatures. The configurable input range matches typical LNA output levels in ultrasound front-ends. Placed after the time-gain-compensation (TGC) amplifier and before the beamforming DSP, the ADC converts each scan line into a digital stream at the ultrasound pulser repetition rate; the pipelined latency is well within the real-time beamforming budget for medical imaging applications.
推荐
Portable Test and Measurement Instrumentation
Portable test and measurement instruments benefit from the THS1040CPWRG4's low-power single 3 V supply operation, 40 MSPS rate, and 10-bit resolution that suits digitizing oscilloscope channels and data acquisition inputs in handheld meters. The 60 dB SNR preserves measurement accuracy for moderate-precision instruments, and the small TSSOP-28 package fits densely populated handheld PCBs. Used as the primary ADC in a portable oscilloscope or spectrum analyzer, the part digitizes the conditioned analog input at up to 40 MSPS and presents the data to a microcontroller or DSP for FFT and display processing; the G4 Pb-free finish ensures compliance with portable consumer electronics environmental regulations.
推荐
推荐产品汇总
工程参考数据： THS1040CPWRG4 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | THS1041CPWRG4 | THS1040CPWR | THS1040IPWR | THS1031IPWRG4 | THS1031IPWG4 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | TSSOP-28 (PW) | TSSOP-28 (PW) - same | TSSOP-28 (PW) - same | TSSOP-28 (PW) - same | TSSOP-28 (PW) - same | TSSOP-28 (PW) - same |
| Sampling Rate | 40 MSPS | 60 MSPS | 40 MSPS | 40 MSPS | 30 MSPS | 30 MSPS |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Supply Voltage | 3 V analog / 3 V digital | 3 V analog / 3 V digital | 3 V analog / 3 V digital | 3 V analog / 3 V digital | 3 V analog / 3 V digital | 3 V analog / 3 V digital |
| Temperature Range | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Pb-Free Finish | Yes (G4 suffix) | Yes (G4 suffix) | Non-G4 finish | Non-G4 finish | Yes (G4 suffix) | Yes (G4 suffix) |
| Input Configuration | Single-ended or differential | Single-ended or differential | Single-ended or differential | Single-ended or differential | Single-ended or differential | Single-ended or differential |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Approximate Unit Price (qty 1) | $6.50 | $7.20 | $6.30 | $8.50 | $5.80 | $5.60 |
关键差异点
- Single 3 V supply operation with low power （对比 Industry typical 5 V ADCs)
- Configurable input range with built-in reference （对比 External-reference-only ADCs)
- Same-package upgrade path to 60 MSPS （对比 THS1031IPWRG4 (30 MSPS lower tier))
- Pb-free G4 finish for RoHS compliance （对比 Legacy Pb-finish ADC versions)
设计说明
The THS1040CPWRG4 requires a low-noise 3 V analog supply (AVDD) and a separate 3 V digital supply (DVDD). Decouple each supply pin with a 10 uF tantalum bulk capacitor plus a 0.1 uF ceramic capacitor placed within 5 mm of the supply pins. Use separate analog and digital ground planes connected at a single point near the ADC to prevent digital switching noise from coupling into the analog input. The PD (power-down) pin reduces supply current to a few hundred microamps when the ADC is not in use, valuable in battery-powered designs.
Place the analog input traces (AIN+, AIN-) on the top layer with a contiguous ground reference plane underneath to maintain 50-ohm characteristic impedance and minimize crosstalk. Keep the digital output bus traces (D0-D9) routed away from the analog input traces to prevent digital noise coupling. Use matched trace lengths on the clock input to avoid sampling jitter, and place the clock driver within 25 mm of the CLK pin. The reference decoupling capacitors on REFT, REFB, REFCM must be placed within 3 mm of their respective pins with low-ESR ceramic types.
Drive the analog input differentially for best SFDR performance: a differential driver such as the THS4503 or THS4511 will deliver 3-6 dB better SFDR than single-ended drive at the same clock rate. Configure the input full-scale range via the VREF pin: 1 Vp-p for low-noise operation, 2 Vp-p for maximum dynamic range. Maintain clock duty cycle at 50% +/- 5% to avoid spurious harmonics at odd multiples of the sample rate. The OE (output enable) pin allows tri-state control of the digital output bus, useful in multi-ADC parallel configurations.
合规信息
G4 suffix denotes Pb-free matte-tin finish compliant with RoHS directive. Commercial temperature grade (0C to +70C). AEC-Q100 not applicable for commercial-grade ADC.
