THS1031IPWRG4 - 10-Bit 30MSPS ADC Single Ch. TSSOP-28 | Texas Instruments
料号： THS1031IPWRG4 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $6.32 | $6.32 |
| 10 | $5.71 | $57.10 |
| 100 | $4.78 | $478.00 |
| 500 | $4.05 | $2,025.00 |
| 1,000 | $3.42 | $3,420.00 |
THS1031IPWRG4 概述
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes; within the broader ADC hierarchy, the THS1031 sits as a pipelined successive-stage ADC, a subfamily of data converters that achieves high sample rates (tens of MSPS) at moderate resolution (8-12 bits), falling under data conversion ICs and the parent category of signal-chain semiconductors. Pipelined ADCs balance speed, power, and resolution for applications like video, communications, and industrial imaging.
Key technical features include 10-bit resolution at 30 MSPS, configurable input functions (single-ended, single-ended with analog clamp, single-ended with programmable digital clamp, differential), integrated programmable gain amplifier (PGA), built-in programmable digital clamp, out-of-range indicator, low-power powerdown mode, single +3V analog supply operation, and an external reference input. The TSSOP-28 package supports surface-mount assembly with gull-wing leads.
The THS1031 uses a multi-stage pipelined architecture with internal sample-and-hold and error-correction logic to achieve 30 MSPS throughput at 10-bit resolution. Internal registers accessed through a serial interface configure input mode, gain, clamp level, and powerdown state. The wide analog input range and configurable PGA make the converter adaptable to many sensor and signal-conditioning front ends.
Typical applications include digital video processing, set-top boxes, CCD imaging scanners, digital still cameras, portable instrumentation, and IF/baseband communications digitizers. The integrated clamp and gain are particularly useful in video digitization where DC restoration and signal scaling must occur ahead of the ADC.
A key design consideration is input bandwidth versus sample-rate: at 30 MSPS, the analog input bandwidth must support the relevant Nyquist zone without attenuation. Decoupling the analog supply with 0.1 uF and 10 uF capacitors placed within 5 mm of the AVDD pin is critical for achieving the rated SNR.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on a single manufacturer datasheet page.
直接替换替代料： THS1031IPWRG4 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： THS1031IPWRG4 （相同外形与封装尺寸） ——差异在于 Package, Architecture, RoHS Status, Operating Temperature Range, Resolution.
快速对比工具——选择替代料号进行并排对比：
THS1031IPWG4
✅ 直接替换✓ 有现货
$3.38 / 个
查看数据手册 →THS1031IDWR
✅ 直接替换✓ 有现货
$5.55 / 个
查看数据手册 →THS1031IPWR
✅ 直接替换📋 参考替代料（不在目录中）
THS1030CDWRG4
✅ 直接替换📋 参考替代料（不在目录中）
THS1032CPWR
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ADS902E
✅ 直接替换📋 参考替代料（不在目录中）
ADC1173CIVS/NOPB
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
THS1031IPWRG4 最大额定值与电气特性
| 分辨率 | 10 bits |
| Sample Rate | 30 MSPS |
| Number of Channels | 1 channel |
| Architecture | Pipelined |
| Input Type | Single-ended / Differential (configurable) |
| Analog Supply Voltage | 3 V (typical, single supply) |
| Input Configuration Modes | Single-ended, SE + analog clamp, SE + digital clamp, differential |
| Integrated PGA | Yes, programmable gain |
| Digital Clamp | Yes, programmable |
| Out-of-Range Indicator | Yes |
| Powerdown Mode | Yes |
| Reference | External |
| Data Interface | Parallel CMOS |
| 封装 | TSSOP-28 (PW) 9.7 mm x 4.4 mm |
| Terminal Form | Gull Wing |
| Temperature Grade | Industrial (-40C to +85C) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
THS1031IPWRG4 引脚配置
| 引脚 1 | AVDD — Analog supply voltage |
| 引脚 2 | AVSS — Analog ground |
| 引脚 3 | IN+ — Positive analog input |
| 引脚 4 | IN- — Negative analog input (for differential) |
| 引脚 5 | REFT — Top reference decoupling |
| 引脚 6 | REFB — Bottom reference decoupling |
| 引脚 7 | VREF — External reference voltage input |
| 引脚 8 | DRVDD — Digital output driver supply |
| 引脚 9 | DRVSS — Digital driver ground |
| 引脚 10 | DB0 — Data bit 0 (LSB) |
| 引脚 11 | DB1 — Data bit 1 |
| 引脚 12 | DB2 — Data bit 2 |
| 引脚 13 | DB3 — Data bit 3 |
| 引脚 14 | DB4 — Data bit 4 |
| 引脚 15 | DB5 — Data bit 5 |
| 引脚 16 | DB6 — Data bit 6 |
| 引脚 17 | DB7 — Data bit 7 |
| 引脚 18 | DB8 — Data bit 8 |
| 引脚 19 | DB9 — Data bit 9 (MSB) |
| 引脚 20 | OOR — Out-of-range indicator |
| 引脚 21 | PD — Powerdown control input |
| 引脚 22 | SCLK — Serial interface clock |
| 引脚 23 | SDATA — Serial interface data |
| 引脚 24 | CS — Chip select for serial interface |
| 引脚 25 | CLK — ADC sample clock input |
| 引脚 26 | DVDD — Digital supply voltage |
| 引脚 27 | DVSS — Digital ground |
| 引脚 28 | NC — Not connected (per datasheet) |
典型应用
THS1031IPWRG4 适用于 6 应用s: Digital Video Processing, CCD Imaging Scanner Digitizer, Set-Top Box IF Sampling, Digital Still Camera Image Pipeline, Portable Instrumentation Data Acquisition, Baseband Communications Digitizer.
Digital Video Processing
The THS1031IPWRG4's 10-bit resolution and 30 MSPS throughput make it well suited for digitizing composite or component video signals in set-top boxes, DVD recorders, and video capture cards. The integrated analog clamp performs DC restoration at the back porch, eliminating external op-amp clamp circuits, while the programmable digital clamp and gain handle fine-scale video levels before sampling. According to TI's THS1031 datasheet, the pipelined architecture sustains 30 MSPS on a single 3 V rail, so the converter fits portably powered video appliances. Use a 6 dB pre-emphasis network on the analog input to compensate for cable losses.
推荐
CCD Imaging Scanner Digitizer
The THS1031IPWRG4's 30 MSPS sample rate matches the pixel clock of medium-resolution line-scan CCD imagers commonly used in document scanners, industrial inspection cameras, and barcode readers. Its differential input mode rejects common-mode noise picked up on long CCD cable assemblies, while the integrated programmable gain stage compensates for the CCD's responsivity variation across channels. The 10-bit dynamic range captures the typical 60+ dB CCD signal-to-noise ratio of office-lighting scanners. Decouple the analog supply within 5 mm of the AVDD pin to preserve SNR at full throughput.
推荐
Set-Top Box IF Sampling
The THS1031IPWRG4 supports undersampling of IF (intermediate-frequency) signals in digital cable and satellite set-top boxes, where its analog input bandwidth exceeds 100 MHz and its 30 MSPS sample rate is sufficient for low-IF digitization. The converter's pipelined architecture preserves sufficient SNR for QAM demodulation downstream, and its powerdown mode reduces standby current during user inactivity. The TSSOP-28 package integrates directly into tuner modules without adding excessive board height. Differential inputs reject common-mode noise from switching power supplies on the main board.
推荐
Digital Still Camera Image Pipeline
The THS1031IPWRG4's 10-bit resolution at 30 MSPS captures CCD/CMOS image sensor output streams in entry-level digital still cameras at burst-rate frame capture. The integrated programmable gain stage adjusts per-frame to handle varying scene brightness, and the digital clamp removes sensor dark-current offset before white-balance processing. A single 3 V analog supply simplifies power-tree design versus discrete 5V+3V designs. The TSSOP-28 industrial-grade package supports operation from -40C to +85C for consumer and prosumer camera enclosures.
推荐
Portable Instrumentation Data Acquisition
The THS1031IPWRG4's single +3 V operation, integrated gain, and 30 MSPS throughput suit portable battery-powered oscilloscopes, data loggers, and field instruments. Its powerdown mode drops quiescent current between triggered acquisitions, extending battery life in handhelds. The TSSOP-28 package fits into pocket-sized instruments where height is at a premium, and the 10-bit resolution captures transient waveforms at sub-microsecond resolution. Program the onboard digital clamp to suppress DC drift in long-duration captures.
推荐
Baseband Communications Digitizer
The THS1031IPWRG4 digitizes baseband I/Q signals in software-defined radio (SDR) receivers and baseband signal processing cards at 30 MSPS, supporting 15 MHz Nyquist bandwidth. Its pipelined architecture handles modern QAM and OFDM waveforms with sufficient spurious-free dynamic range, while the integrated PGA aligns full-scale inputs from sub-zero dBm RF front ends. Differential inputs reject ground-loop noise in chassis-mounted communications equipment. Use a low-jitter clock source for the sample clock to maximize SFDR at full rate.
推荐
推荐产品汇总
工程参考数据： THS1031IPWRG4 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | THS1031IPWG4 | THS1031IDWR | THS1030CDWRG4 | THS1032CPWR | ADS902E |
|---|---|---|---|---|---|---|
| Package | TSSOP-28 (PW) | TSSOP-28 (PW) - same | TSSOP-28 (PW) - same | SOIC-28 (DW) | TSSOP-28 (PW) - same | SSOP-28 (28-pin) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 12 bits | 10 bits |
| Sample Rate | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Integrated PGA | Yes | Yes | Yes | Yes | Yes | No |
| Digital Clamp | Yes | Yes | Yes | Yes | Yes | No |
| Out-of-Range Indicator | Yes | Yes | Yes | Yes | Yes | No |
| Powerdown Mode | Yes | Yes | Yes | Yes | Yes | Yes |
关键差异点
- Integrated PGA + analog/digital clamp in a 28-pin TSSOP （对比 ADS902E)
- Single 3 V supply operation （对比 ADS825E/1K)
- Out-of-range indicator for automatic gain control （对比 THS1030CDWRG4)
设计说明
Decouple the analog supply (AVDD) with a 0.1 uF ceramic capacitor in parallel with a 10 uF tantalum or ceramic capacitor within 5 mm of the AVDD pin. The driver supply (DRVDD) requires an identical LC-PI filter to keep switching transients off the analog rail. According to TI's THS1031 datasheet, sharing analog and digital ground is acceptable if the connection is single-point at the ADC's exposed pad, otherwise use a ground split with a ferrite bead at the single tie point.
Route analog input traces as a 100 ohm differential pair with ground shielding on both sides, keeping trace length under 25 mm to limit crosstalk. Place the external reference capacitor (VREF) directly at the VREF pin with a short stub to AVSS. The 28-lead TSSOP's exposed thermal pad (if present) must be soldered to a copper pour tied to AVSS for thermal and electrical return.
Exceeding the maximum analog input range of +/- VREF causes saturation that can take several sample clocks to recover. Always clamp the analog front end to within the THS1031's absolute maximum ratings, especially during hot-plug events. The PD (powerdown) pin must be driven low to enable sampling; a floating PD pin leaves the chip in undefined state - use a 100 kohm pull-down to AVSS if not actively driven.
Estimated: For an 8 dBm fundamental at 10 MHz IF, broadband noise floor of -72 dBFS at 30 MSPS gives 70 dB SINAD at the THS1031's differential input. Use a low-jitter (<5 ps RMS) clock source for the ADC sample clock; higher jitter degrades SNR by approximately 20*log10(jitter_period/1 ns).
合规信息
RoHS compliant per TI product page. The '-G4' suffix denotes Pb-free green packaging. Industrial temperature grade, not AEC-Q100 qualified; not suitable for automotive under-hood applications.
