EP1K10TC100-2 vs EP1K10TC100-3N مقارنة
مقارنة تفصيلية جنبًا إلى جنب لـ EP1K10TC100-2 بواسطة Intel و EP1K10TC100-3N بواسطة Intel. قارن المواصفات الرئيسية والمعلمات الكهربائية والتغليف وحالة دورة الحياة والأسعار والتوافر لتحديد أفضل مكوّن لمتطلبات تصميمك.
Intel
EP1K10TC100-3N - 10K-Gate ACEX-1K FPGA, 576 Cells, 66 I/O, 100-TQFP | Intel / Altera
EP1K10TC100-3N Obsoleteمقارنة المواصفات
| المعامل | EP1K10TC100-2 | EP1K10TC100-3N |
|---|---|---|
| العلامة التجارية | Intel | Intel |
| الفئة | FPGA & CPLD | FPGA & CPLD |
| حالة دورة الحياة | Obsolete | Obsolete |
| Family | ACEX-1K | ACEX 1K |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements / Cells | 576 | — |
| Number of Logic Array Blocks (LABs/CLBs) | 72 | — |
| Total RAM Bits | 12288 | — |
| Number of Gates | 10000 (typical); 56000 (maximum) | — |
| Number of User I/O | 66 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Pin-to-Pin Logic Delay | 0.5 ns | — |
| Maximum Internal Frequency | 200 MHz (per FPGAkey listing) | — |
| Process Technology | 0.22 μm CMOS | 0.22 µm CMOS |
| Core Supply Voltage (VCCINT) | 2.375 V to 2.625 V (2.5 V nominal) | — |
| I/O Supply Voltage (VCCIO) | [DATA_NEEDED: VCCIO range] | — |
| درجة حرارة التشغيل | 0 °C to 70 °C (TA, commercial) | [DATA_NEEDED: operating temperature range] |
| العلبة | 100-pin TQFP (TQFP-100) | 100-pin TQFP |
| نوع التركيب | Surface Mount | — |
| Configuration Method | SRAM, serial / JTAG (IEEE 1149.1) | — |
| حالة RoHS | Compliant (per Heisener / DigiKey listings) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes | — |
| Series | — | ACEX-1K |
| Manufacturer | — | Intel (formerly Altera) |
| Typical Gate Count | — | 10,000 gates |
| Logic Elements (Cells) | — | 576 |
| Embedded Memory (EAB) | — | 12,288 bits |
| Number of LABs | — | 72 |
| User I/O Count | — | 66 |
| Operating Voltage (Core) | — | 2.5 V |
| Maximum Internal Clock Frequency | — | 200 MHz |
| Speed Grade | — | -3 (commercial) |
| JTAG Support | — | Yes (IEEE 1149.1-1990) |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (5.0 V) |
| Configuration | — | JTAG / serial configuration device |