EP2A25F672I6 vs EP2A25F672I-9 مقارنة
مقارنة تفصيلية جنبًا إلى جنب لـ EP2A25F672I6 بواسطة Intel و EP2A25F672I-9 بواسطة Intel. قارن المواصفات الرئيسية والمعلمات الكهربائية والتغليف وحالة دورة الحياة والأسعار والتوافر لتحديد أفضل مكوّن لمتطلبات تصميمك.
مقارنة المواصفات
| المعامل | EP2A25F672I6 | EP2A25F672I-9 |
|---|---|---|
| العلامة التجارية | Intel | Intel |
| الفئة | FPGA & CPLD | FPGA & CPLD |
| حالة دورة الحياة | NRND | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements (typical gates) | 25,000 | — |
| Fabric Architecture | SRAM-based LUT | — |
| Process Technology | 0.18 µm CMOS | 0.18 µm CMOS |
| العلبة | 672-ball FineLine BGA (FBGA-672) | 672-pin FCBGA (FineLine BGA) |
| Core Voltage | 1.5 V | 1.5 V / 1.8 V (speed-grade dependent) |
| Configuration Method | External SRAM configuration device (EPC series) | JTAG / serial configuration EPROM |
| Temperature Grade | Industrial (-40 °C to +100 °C ambient) | — |
| Speed Grade | 6 | -9 |
| Embedded Memory | Embedded System Blocks (ESB), dual-port RAM / CAM | — |
| DSP Blocks | MultiCore dedicated multipliers | — |
| Boundary Scan | JTAG (IEEE 1149.1) compliant | — |
| Clock Management | Dedicated PLL / clock tree circuitry | — |
| I/O Bank Count | [DATA_NEEDED: number of user I/O banks] | — |
| حالة RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| مستوى MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| نوع التركيب | Surface Mount (BGA) | Surface Mount (BGA) |
| Logic Elements (typical) | — | 25,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Operating Temperature Grade | — | Industrial (-40 °C to +100 °C junction) |
| مستوى حساسية الرطوبة (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |