EP910DM-40 vs EP910IDI-15 مقارنة
مقارنة تفصيلية جنبًا إلى جنب لـ EP910DM-40 بواسطة Altera و EP910IDI-15 بواسطة Altera. قارن المواصفات الرئيسية والمعلمات الكهربائية والتغليف وحالة دورة الحياة والأسعار والتوافر لتحديد أفضل مكوّن لمتطلبات تصميمك.
مقارنة المواصفات
| المعامل | EP910DM-40 | EP910IDI-15 |
|---|---|---|
| العلامة التجارية | Altera | Altera |
| الفئة | FPGA & CPLD | FPGA & CPLD |
| حالة دورة الحياة | Obsolete | Obsolete |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | Classic EPLD |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | — |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | — |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| العلبة | 40-pin Ceramic DIP (Cerdip) with UV window | 40-pin CDIP (CerDIP) with quartz window |
| نوع التركيب | Through-Hole (DIP) | Through-hole (DIP) |
| درجة حرارة التشغيل | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial, "I" grade) |
| جهد التغذية | 5 V | — |
| حالة RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 gates |
| Maximum User I/O Pins | — | 36 |
| Pin-to-Pin Propagation Delay (tpd) | — | 15 ns |
| Maximum Counter Frequency | — | 66.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS EPROM |
| Program/Erase Method | — | UV-erasable windowed CerDIP |
| Macrocells Configurable As | — | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | — | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | — | Altera Logic Programmer card |
| Logic Family Compatibility | — | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |