EP910IDC-15 vs EP910DI-35 مقارنة
مقارنة تفصيلية جنبًا إلى جنب لـ EP910IDC-15 بواسطة Altera و EP910DI-35 بواسطة Altera. قارن المواصفات الرئيسية والمعلمات الكهربائية والتغليف وحالة دورة الحياة والأسعار والتوافر لتحديد أفضل مكوّن لمتطلبات تصميمك.
مقارنة المواصفات
| المعامل | EP910IDC-15 | EP910DI-35 |
|---|---|---|
| العلامة التجارية | Altera | Altera |
| الفئة | FPGA & CPLD | FPGA & CPLD |
| حالة دورة الحياة | Obsolete | نشط |
| Manufacturer | Altera (now Intel PSG) | Original Altera; long-term authorized by Rochester Electronics, LLC |
| Family | Classic EPLD | Altera Classic EPLD |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| العلبة | 40-pin CDIP (Ceramic DIP, through-hole) | CDIP-40 (Ceramic DIP with UV window) |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 10 | 10 |
| Programming Technology | EPROM (UV-erasable) | — |
| حالة RoHS | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency (fCNT) | — | 28.6 MHz |
| Supply Current (ICC) | — | 40 mA typical |
| Bidirectional I/O Pins | — | 20 |
| Total Pins | — | 40 |
| نوع التركيب | — | Through-Hole |
| درجة حرارة التشغيل | — | -40C to +85C (industrial) |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | EPROM programmer + JEDEC fuse map |
| Erasure Method | — | UV light through quartz window |
| Logic Family | — | PAL-type AND/OR array with D flip-flops |