EP910IDC-15 vs EP910DI-35 Perbandingan

Perbandingan bersamaan detil EP910IDC-15 dari Altera dan EP910DI-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP910IDC-15 EP910DI-35
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Aktif
Manufacturer Altera (now Intel PSG) Original Altera; long-term authorized by Rochester Electronics, LLC
Family Classic EPLD Altera Classic EPLD
Equivalent Gates 450 —
Macrocells 24 24
Flip-Flops 48 —
Pin-to-Pin Delay (tPD) 15 ns —
Maximum Frequency (fCNT) 66.6 MHz —
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V nominal)
Paket 40-pin CDIP (Ceramic DIP, through-hole) CDIP-40 (Ceramic DIP with UV window)
Terminal Count 40 —
Terminal Form Through-Hole —
Temperature Grade Commercial (0C to +70C) —
Programmable Security Bit Yes —
On-board Test Circuitry Yes —
Logic Type UV Erasable EPROM-based —
I/O Pins 24 —
Dedicated Inputs 10 10
Programming Technology EPROM (UV-erasable) —
Status RoHS non_compliant (ceramic DIP contains lead) [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Product Type — EPLD (Erasable Programmable Logic Device)
Usable Gates — 450
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Current (ICC) — 40 mA typical
Bidirectional I/O Pins — 20
Total Pins — 40
Tipe Mounting — Through-Hole
Suhu Kerja — -40C to +85C (industrial)
Technology — CMOS, UV-erasable EPROM
Programming Method — EPROM programmer + JEDEC fuse map
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops

Spek dan Sumber

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