LTC2280CUP - Dual 10-Bit 105Msps Low-Noise 3V ADC | Analog Devices
MPN: LTC2280CUP ✓ Hoạt độngLTC2280CUP Tóm tắt
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog signals and quantises them into discrete digital codes. Pipelined ADCs convert a single sample in multiple low-resolution stages, enabling high sampling rates at moderate power; within the broader taxonomy they belong to data-converter ICs, then data acquisition, then signal-chain semiconductors. The LTC2280CUP sits in the dual-channel, low-voltage, medium-resolution segment of this hierarchy.
Key specifications include 61.6 dB signal-to-noise ratio (SNR) at 14 MHz input, 73 dB spurious-free dynamic range (SFDR), and an input-referred noise of 0.96 LSBrms. Each channel features its own track-and-hold amplifier, an internal reference, and a three-state digital output bus. Differential inputs are supported, and the device accepts both single-ended and differential drive topologies. Power-down, out-of-range, and data-ready indicators simplify system integration with FPGAs and DSPs.
Typical applications include dual-channel digital oscilloscopes and data acquisition front-ends, IF sampling for software-defined radio (SDR) and cellular base stations, medical ultrasound beamforming arrays, and dual-stream CCD or CMOS imaging pipelines. The 3V analog supply and LVCMOS/LVDS-compatible outputs ease interface to modern low-voltage FPGAs and ASICs.
When designing with this device, allocate generous ground and power planes around the 64-pin QFN exposed pad to manage thermal dissipation (about 1.2W at 105 Msps, dual channel). Use 0.1 uF ceramic bypass capacitors within 5 mm of every supply pin, and route the analog inputs as 50 ohm-controlled-impedance differential pairs to preserve SNR at the 70 MHz input bandwidth.
Bộ thay thế dễ dàng lắp đặt cho LTC2280CUP — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2280CUP (cùng hình factor và footprint) — khác nhau ở Package, SFDR, SNR, RoHS Status, Input Type.
LTC2280IUP
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
LTC2221CUP
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2155CUP-12
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2150CUJ-14
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2180CUP
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2280CUP Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 10 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 105 Msps per channel |
| Architecture | Pipelined |
| Input Type | Differential / single-ended |
| Supply Voltage (Analog) | 3 V (2.85 V to 3.4 V) |
| Supply Voltage (Digital) | 3 V |
| Power Dissipation (typical) | 250 mW at 105 Msps, both channels |
| SNR (14 MHz input) | 61.6 dB |
| SFDR | 73 dB |
| Input-Referred Noise | 0.96 LSBrms |
| Input Bandwidth | 70 MHz |
| Output Format | LVCMOS (parallel) |
| Khoảng nhiệt độ hoạt động | 0 C to +70 C (commercial grade) |
| Hộp | 64-pin QFN (9x9 mm) with exposed pad |
| Trạng thái RoHS | Compliant (lead-free #PBF suffix) |
Cấu hình chân LTC2280CUP
| Chân 1 | OGND — Output buffer ground reference |
| Chân 2 | DVDD — 3V digital supply |
| Chân 3 | D1B_0 — Channel B digital output bit 0 (LSB) |
| Chân 4 | D1B_1 — Channel B digital output bit 1 |
| Chân 5 | D1B_2 — Channel B digital output bit 2 |
| Chân 6 | D1B_3 — Channel B digital output bit 3 |
| Chân 7 | D1B_4 — Channel B digital output bit 4 |
| Chân 8 | D1B_5 — Channel B digital output bit 5 |
| Chân 9 | D1B_6 — Channel B digital output bit 6 |
| Chân 10 | D1B_7 — Channel B digital output bit 7 |
| Chân 11 | D1B_8 — Channel B digital output bit 8 |
| Chân 12 | D1B_9 — Channel B digital output bit 9 (MSB) |
| Chân 13 | OGND — Output buffer ground |
| Chân 14 | OFB — Channel B out-of-range flag |
| Chân 15 | OGND — Output buffer ground |
| Chân 16 | DVDD — 3V digital supply |
| Chân 17 | CLKOUTB — Channel B clock output (data ready) |
| Chân 18 | OGND — Output buffer ground |
| Chân 19 | CLKOUTA — Channel A clock output (data ready) |
| Chân 20 | DVDD — 3V digital supply |
| Chân 21 | OFA — Channel A out-of-range flag |
| Chân 22 | OGND — Output buffer ground |
| Chân 23 | D1A_0 — Channel A digital output bit 0 (LSB) |
| Chân 24 | D1A_1 — Channel A digital output bit 1 |
| Chân 25 | D1A_2 — Channel A digital output bit 2 |
| Chân 26 | D1A_3 — Channel A digital output bit 3 |
| Chân 27 | D1A_4 — Channel A digital output bit 4 |
| Chân 28 | D1A_5 — Channel A digital output bit 5 |
| Chân 29 | D1A_6 — Channel A digital output bit 6 |
| Chân 30 | D1A_7 — Channel A digital output bit 7 |
| Chân 31 | D1A_8 — Channel A digital output bit 8 |
| Chân 32 | D1A_9 — Channel A digital output bit 9 (MSB) |
| Chân 33 | OGND — Output buffer ground |
| Chân 34 | DVDD — 3V digital supply |
| Chân 35 | CLK — External clock input |
| Chân 36 | OE — Output enable (active high) |
| Chân 37 | SHDN — Power-down control (active high) |
| Chân 38 | REFT — Internal reference top |
| Chân 39 | REFB — Internal reference bottom |
| Chân 40 | REFOUT — Internal reference output (1.5V typical) |
| Chân 41 | SENSE — Reference programming pin |
| Chân 42 | AGND — Analog ground reference |
| Chân 43 | AVDD — 3V analog supply |
| Chân 44 | VCM — Common-mode voltage output (1.5V) |
| Chân 45 | AIN2+ — Channel 2 positive analog input |
| Chân 46 | AIN2- — Channel 2 negative analog input |
| Chân 47 | AGND — Analog ground |
| Chân 48 | AVDD — 3V analog supply |
| Chân 49 | AIN1+ — Channel 1 positive analog input |
| Chân 50 | AIN1- — Channel 1 negative analog input |
| Chân 51 | VCM — Common-mode voltage output |
| Chân 52 | AVDD — 3V analog supply |
| Chân 53 | AGND — Analog ground |
| Chân 54 | AGND — Analog ground |
| Chân 55 | AVDD — 3V analog supply |
| Chân 56 | AGND — Analog ground |
| Chân 57 | AVDD — 3V analog supply |
| Chân 58 | AGND — Analog ground |
| Chân 59 | AVDD — 3V analog supply |
| Chân 60 | AGND — Analog ground |
| Chân 61 | AVDD — 3V analog supply |
| Chân 62 | AGND — Analog ground |
| Chân 63 | DVDD — 3V digital supply |
| Chân 64 | OGND — Output buffer ground |
Ứng dụng tiêu biểu
LTC2280CUP phù hợp cho 6 Áp dụngs: Dual-Channel IF Sampling for Software-Defined Radio, Medical Ultrasound Beamforming Front-End, Dual-Stream CCD/CMOS Image Acquisition, Communications Test and Measurement Instrumentation, Multi-Channel Data Acquisition Front-End, Radar and Lidar Baseband Digitisation.
Dual-Channel IF Sampling for Software-Defined Radio
The LTC2280CUP's dual-channel 105 Msps sampling and 70 MHz input bandwidth make it ideal for IF digitisation in software-defined radio receivers. Its 61.6 dB SNR at 14 MHz input preserves modulation accuracy on 64-QAM signals, while the matched dual channels allow I/Q baseband or diversity reception in a single IC. Place the ADC downstream of a 2-stage IF filter chain; supply 3V from a low-noise LDO like the LT3042 to avoid corrupting SNR. Unlike a discrete 2-ADC solution, the matched internal track-and-hold amplifiers eliminate gain and offset mismatches that would otherwise require per-channel calibration.
Được đề xuất
Medical Ultrasound Beamforming Front-End
In ultrasound beamforming arrays, the LTC2280CUP simultaneously samples multiple receive channels at 105 Msps, enabling digital beamforming across a 32- or 64-element transducer array. The 73 dB SFDR rejects harmonic distortion from piezoelectric transducers, preserving image contrast, while the 10-bit resolution is sufficient for B-mode imaging where dynamic range is limited by the tissue interface. Mount the QFN-64 with a continuous copper ground plane under the exposed pad to dissipate 250 mW without thermal throttling. Per-channel digital outputs connect directly to an FPGA for delay-and-sum beamforming.
Được đề xuất
Dual-Stream CCD/CMOS Image Acquisition
Industrial and scientific cameras use the LTC2280CUP to digitise two parallel image sensor streams at 105 Msps per channel, supporting up to 10K line-rate CCD sensors when pixel clocking exceeds 100 MHz. The dual channels enable simultaneous capture of red/blue or colour-stereo image pairs without external multiplexing, halving the FPGA pin count. The 64-pin QFN (9x9) package fits in space-constrained camera heads, and the 3V single supply aligns with modern CMOS sensor rails. Use matched-length routing on the parallel digital outputs to minimise channel-to-channel skew below one clock period.
Được đề xuất
Communications Test and Measurement Instrumentation
The LTC2280CUP serves dual roles in test equipment: capturing wideband signals in a digitising oscilloscope channel, and providing a second matched channel for trigger/synchronisation paths. Its 61.6 dB SNR supports 10-bit ENOB measurement at 14 MHz, while 73 dB SFDR is adequate for spectral purity tests on RF stimuli. Per-channel power-down reduces consumption to <50 mW when only one channel is in use during calibration routines. Pair the ADC with an FPGA implementing a custom FFT engine; the parallel LVCMOS outputs eliminate the latency of serial LVDS interfaces used in higher-end parts.
Được đề xuất
Multi-Channel Data Acquisition Front-End
Factory automation and process control systems use the LTC2280CUP as a dual-channel digitiser for vibration, acoustic, or strain-gauge signals sampled at 105 Msps. The simultaneous sampling eliminates phase skew between channels, critical for cross-correlation analysis in modal testing. With differential inputs, the ADC rejects 50/60 Hz line noise common in industrial environments, and the 3V single supply simplifies integration into PLC backplanes. Combined with a microcontroller or FPGA for FIR filtering, the LTC2280CUP delivers a compact, low-power data acquisition subsystem.
Được đề xuất
Radar and Lidar Baseband Digitisation
Automotive radar and lidar baseband processors use the LTC2280CUP to digitise I and Q signals from the IF strip at up to 105 Msps, supporting bandwidths of 50 MHz or more for high-resolution ranging. The 73 dB SFDR preserves target discrimination across the radar dynamic range, while the matched dual channels keep I/Q gain and offset matched within the ADC itself. Operating from a single 3V supply, the ADC integrates into compact sensor modules where size and power are constrained. The exposed-pad QFN-64 package allows direct PCB thermal management with copper pours.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2280CUP — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2280IUP | LTC2221CUP | LTC2155CUP-12 | LTC2150CUJ-14 | LTC2180CUP |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9) | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same |
| Resolution | 10 bit | 10 bit | 12 bit | 12 bit | 14 bit | 16 bit |
| Sample Rate | 105 Msps | 105 Msps | 135 Msps | 170 Msps | 105 Msps | 105 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Supply Voltage | 3V (2.85V-3.4V) | 3V (2.85V-3.4V) | 3V (2.85V-3.4V) | 3.5V | 3.5V | 3.5V |
| SNR (14 MHz input) | 61.6 dB | 61.6 dB | 67.5 dB | 68 dB | 72 dB | 76 dB |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
Bảo phân biệt quan trọng
- True dual-channel simultaneous sampling in a single 64-QFN IC (vsLTC2221CUP)
- 10-bit resolution at 105 Msps with 73 dB SFDR (vsLTC2280IUP)
- Drop-in compatible with 12/14/16-bit upgrade path on same footprint (vsLTC2155CUP-12, LTC2150CUJ-14, LTC2180CUP)
Ghi chú thiết kế
The 64-pin QFN package has a centre exposed thermal pad that MUST be soldered to a clean, unbroken analog ground plane to achieve specified thermal and electrical performance. Use an array of thermal vias (0.3 mm drill, 0.5 mm pitch) under the pad to spread heat to inner ground layers. Place 0.1 uF X7R ceramic bypass capacitors within 3 mm of every AVDD and DVDD pin, with a single 10 uF tantalum bulk capacitor near the analog supply entry point.
Do not route digital output traces (D1A_0..9, D1B_0..9, OFA, OFB) under the analog input pins or across the analog ground plane; this couples switching noise into the input and degrades SNR by 5-10 dB. Use matched-length routing within each channel group (length matching within 1 mm) to minimise channel-to-channel skew. Drive the CLK input with a low-jitter (< 5 ps RMS) source; CLK jitter directly degrades SNR according to SNR = 20*log10(1 / (2*pi*f_in*jitter)).
For optimal 73 dB SFDR performance, drive the analog inputs differentially using a transformer (e.g., Mini-Circuits ADT1-1WT) or a differential driver such as the LTC6409. Single-ended drive typically loses 5-8 dB of SFDR due to even-order distortion. Terminate the analog inputs with 100 ohm differential across AIN+ and AIN- to set the input impedance and avoid standing waves on the analog traces.
Estimated: at 105 Msps dual-channel operation, total power dissipation is approximately 250 mW. Derive the analog 3V supply from a low-noise LDO such as the LT3042 or LT1763 rather than the switching regulator directly; switching ripple on AVDD reduces SNR by 3-6 dB per 10 mV of ripple. Use separate analog and digital ground planes joined only at a single point beneath the exposed pad.
Thông tin tuân thủ
RoHS and lead-free compliance confirmed by the #PBF suffix on the Analog Devices part number; non-PBF variant is older lead-containing stock. Halogen-free per the LTC2280CUP material declaration on the Analog Devices product page.
