Memory ICs
Subcategories
Products (476)
EPC16UI88AA - 16Mb Enhanced Config Flash 88-UBGA | Intel
The Intel EPC16UI88AA is a 16-Mbit (16MX1 organization) enhanced-configuration flash memory designed for configuring Altera/Intel FPGA families such as Stratix, Cyclone, and APEX, housed in an 88-ball UBGA (Ultra-fine-line BGA) package. It supports a 66.7 MHz configuration clock and provides 3-STATE outputs with 100,000 write/erase cycle endurance for in-system reconfiguration via JTAG or serial interfaces. An FPGA configuration memory is a non-volatile storage device that holds the FPGA's bitstream and serially loads it into the FPGA's SRAM configuration cells at power-up. The Enhanced Configuration Device family (EPC4, EPC8, EPC16) sits in the hierarchy: configuration PROM -> configuration memory -> non-volatile memory -> semiconductor IC. These devices eliminated the need for external programming hardware by enabling in-system reprogrammability through JTAG, which dramatically accelerated FPGA development cycles and enabled field-upgradeable designs. Key features include 16-Mbit density organized as 16M x 1 bit, a 3.3V core supply, 66.7 MHz maximum configuration clock frequency, and 3-STATE output control. The device interfaces to FPGAs through a dedicated serial configuration bus and supports JTAG boundary-scan programming for board-level testing. The 88-ball UBGA package provides compact mounting for space-constrained designs. Architecturally, the EPC16UI88AA uses a single-transistor NOR flash cell array with on-chip charge-pump generation and an internal oscillator for self-timed programming. The device is split into multiple configuration pages, allowing pre-stored bitstreams to be selected at reset via dedicated page-select pins, enabling multi-boot FPGA systems that can switch between firmware images in microseconds. Typical applications include Altera/Intel Stratix and Cyclone FPGA configuration storage, multi-image FPGA boot systems, industrial control boards requiring in-field firmware upgrades, and prototyping platforms where iterative bitstream loading is required. The device is pin-compatible with other EPC16 family members and pairs directly with Intel FPGA configuration controllers. Design consideration: maintain the 3.3V VCC within tolerance and route JTAG signals with proper length matching; the EPC16 family is now in NRND (Not Recommended for New Designs) status on many distributor pages, so verify long-term availability before committing to new designs. This page synthesizes Intel/Octopart distributor pricing, same-family drop-in alternatives (EPC16UC88AA, EPC16UC88N), and practical design notes not consolidated in the manufacturer datasheet.
EPC16UI88N - 16Mb In-System Prog Config PROM 88-UBGA | Intel
The Intel (formerly Altera) EPC16UI88N is a 16-Mbit (2 Mbyte) in-system programmable configuration PROM designed to configure very-high-density Altera FPGAs, including Stratix, Cyclone, and APEX families. Housed in an 88-pin Ultra FineLine BGA (UFBGA / UBGA) package measuring 11 mm x 8 mm, this industrial-temperature-grade device operates from a single 3.3 V supply and supports 66.7 MHz configuration clock rates for fast FPGA configuration. What is a configuration PROM? A configuration PROM is a non-volatile memory device that stores the bitstream for an FPGA. At power-up or under user control, the PROM serially or in parallel transfers the bitstream to the target FPGA through a dedicated configuration interface (such as Altera's PS, FPP, or AS modes). Configuration PROMs are part of the broader memory hierarchy: PROM -> non-volatile memory -> memory IC -> integrated circuit. They differ from boot flash in microcontrollers because they speak FPGA-specific protocols and include features like multi-device cascading, decompression, and in-system programming (ISP) via JTAG. Key features of the EPC16UI88N include 16 Mbit density, in-system programmability through IEEE 1149.1 (JTAG), a 3.3 V single-supply core, an industrial operating temperature range of -40 C to +85 C, and built-in support for configuring multiple FPGAs in a daisy chain. The device integrates a flash memory array with a configuration controller on a single die, eliminating the need for external memory. The 88-ball UFBGA package supports high-density routing and is suitable for space-constrained designs. Architecturally, the EPC16 uses a flash-based memory core instead of older EPROM or EEPROM cells, allowing unlimited reconfiguration cycles through JTAG. A configuration controller block manages the serial/parallel data transfer and handles multi-device daisy chaining automatically, simplifying board design when several FPGAs must be loaded from a single chain. Typical applications include configuring Altera Stratix, Cyclone, and APEX series FPGAs in industrial control, telecommunications, and test equipment. The device is also used in prototype development where bitstreams are updated frequently via JTAG. When designing with this part, ensure the configuration clock routing on the PCB is short and matched to avoid signal-integrity issues, and respect the cascade-mode timing when multiple EPC16 devices share a chain.
EPC16UI88T - 16Mb Enhanced Config Device, 88-pin UBGA | Altera
The Intel (formerly Altera) EPC16UI88T is a 16-Mbit enhanced configuration memory device designed to configure SRAM-based look-up-table (LUT) FPGAs in the Altera product family. It is housed in an 88-ball Ultra FineLine BGA (UBGA) package with 0.8 mm pitch and supports 3.3V operation. The part is targeted at replacing multiple legacy PROM devices with a single, in-system programmable flash-based configuration store. An enhanced configuration device (EPC) is a non-volatile flash memory with an Altera-specific serial configuration interface that loads bitstream data into a companion FPGA at power-up, after reconfiguration requests, or via remote in-system programming (ISP). Compared with older EPCS / EPCQ devices, the EPC16 family supports multi-boot, dual-image storage, page-mode decompression and the Altera Passive Parallel (PP) or Passive Serial (AS) configuration schemes, providing a more flexible boot source for Stratix, Cyclone, Arria and other LUT-based Altera devices. Key features of the EPC16UI88T include 16 Mb of usable configuration memory, parallel data compression to fit larger bitstreams into the same flash density, support for multiple FPGA configuration schemes (PS, AS, FPP), and in-system programmability through the JTAG or Active Serial interface. The device supports a standard 4-wire serial interface plus optional parallel data path, and offers dedicated MSEL[2:0] and nCONFIG/nSTATUS control pins for handshaking with the target FPGA. Typical applications include boot configuration for mid-density Altera FPGAs (Cyclone III, Cyclone IV, Stratix II GX and similar generation devices), industrial control and factory automation platforms that require remote firmware upgrade capability, networking line cards and base stations, and test/measurement equipment where multi-image storage enables field-safe rollback. The wide operating temperature range and industrial qualification also suit industrial, military, and aerospace ground systems. When designing with this device, confirm that the target FPGA configuration scheme matches the EPC16 control pin mapping, and observe the 0.8 mm BGA PCB layout rules (laser-drilled vias, microvia stack-ups are recommended for high-density BGA fan-out). Always use the manufacturer-supported Quartus II / Quartus Prime programmer for device programming and verify JTAG chain integrity before ISP operations. This page synthesizes distributor stock and pricing, drop-in package-compatible alternatives, and practical PCB/boot design notes that are not consolidated in the manufacturer datasheet.
EPC16UIC88 - 16Mb Enhanced Configuration Device | Altera/Intel
The Altera (now Intel) EPC16UIC88 is a 16-Mbit Enhanced Configuration Device designed for in-system programming of SRAM-based lookup-table (LUT) FPGAs, housed in an 88-ball Ultra FineLine BGA (UBGA) package. It provides 1M x 16 of non-volatile configuration memory with a parallel CMOS interface, operates from a single 3.3 V supply, and supports JTAG-based IEEE Std 1149.1 in-system programmability for field upgrades without removing the device from the board. An Enhanced Configuration Device (ECD) is a serial-configuration PROM that streams bitstream data into a Stratix, Cyclone, APEX, or other Altera FPGA at FPGA power-up, then enters a low-power standby state. Compared with classic EPCS/EPCQ serial flashes, the EPC16 family supports the proprietary 16-bit parallel FPP (Fast Passive Parallel) configuration mode that older Altera FPGAs required, and integrates the Altera 4-pin passive configuration controller so no external host controller is needed during configuration. The EPC16UIC88 sits in the configuration-memory IC hierarchy: configuration PROM -> serial/parallel configuration memory -> FPGA bitstream storage -> programmable-logic boot device. Key features of the EPC16UIC88 include 16 Mb of flash-organized storage, JTAG-ISP via IEEE 1149.1, a dedicated nCONFIG/nSTATUS/CONF_DONE handshake with the target FPGA, multi-device cascading for systems larger than 16 Mb, and a 20-year data-retention specification. The UBGA-88 11 x 8 mm package supports the JTAG-driven ISP that allows board-level reprogramming of the configuration bitstream in production or in the field, while an internal oscillator and controller offload bitstream-clocking tasks from the system processor. The device uses a CMOS process with a 3.3 V core; during configuration it draws the bulk of its current, then drops to a micro-amp standby once CONF_DONE is asserted. This separation is important because power-sequencing on legacy Altera FPGAs typically requires the configuration PROM to be valid before the FPGA's VCCINT ramp completes, so deterministic PROM power-up timing is part of the design. Typical applications for the EPC16UIC88 include legacy Stratix II/III, Cyclone II/III, APEX 20K, and Mercury FPGA designs where 16 Mb is sufficient, industrial control boards requiring in-field configuration updates via JTAG, and multi-device daisy-chained configurations where two EPC16s combine to provide 32 Mb. It is also used as a fallback boot image in systems that later migrate bitstream loading to a host processor or to a serial flash. When designing with the EPC16UIC88, observe the JTAG chain order, the nCONFIG/nSTATUS pull-up requirements, and the recommended decoupling on VCC (one 0.1 uF plus one bulk capacitor placed within 1 cm of the package). The Altera Enhanced Configuration Device Data Sheet for the EPC4, EPC8, and EPC16 family should be consulted for the cascaded-configuration schematic and for JTAG chain length limits. This page synthesizes Altera/Intel distributor pricing, JTAG-ISP-enabled drop-in alternatives, and practical FPGA-configuration design notes that are not gathered in a single location in the manufacturer's datasheet, giving a board-level engineer the cross-reference and design checklist needed for a one-step ECO.
EPC16VC88 - 16Mb Enhanced Configuration Device | Altera
The Altera EPC16VC88 is a 16-Mbit enhanced configuration device in an 88-pin CQFP package, designed to configure SRAM-based look-up-table (LUT) devices including the Stratix, Cyclone, APEX, and Mercury FPGA families. It integrates a 3.3V flash memory array with an internal configuration controller that streams compressed or uncompressed configuration data to a target FPGA through a serial or parallel interface, eliminating the need for an external PROM and reducing board complexity. An enhanced configuration device is a serial-configuration-class flash memory with an on-chip JTAG controller that automates FPGA bitstream loading. In the system hierarchy it sits between raw non-volatile memory (NOR flash, EEPROM) and the FPGA it configures, providing in-system programmability (ISP) compliant with IEEE Std 1532 draft 2.0. The flash memory stores up to 16 Mbits of configuration data, which is decompressed inside the target FPGA to load a much larger logical bitstream. Key features of the EPC16VC88 include 16-Mbit storage density, a dedicated nCONFIG/nSTATUS/CONF_DONE handshake interface, multi-device cascade support for configuring multiple FPGAs in a chain, and 3.3V single-supply operation. According to the Altera Enhanced Configuration Devices (EPC4, EPC8, EPC16) datasheet, the device supports both serial (1-bit) and parallel (8-bit) configuration modes, with a typical configuration clock rate of 20 MHz in serial mode. ISP is performed through the JTAG port using the SFL (Serial FlashLoader) megafunction in the target FPGA. Architecturally the EPC16VC88 pairs a 3.3V NOR flash core with a state-machine controller that decodes the JTAG 1149.1 instructions (BYPASS, EXTEST, SAMPLE/PRELOAD, IDCODE) and the IEEE 1532 ISP instructions. The controller manages page erase, program, and verify operations on the flash array, and presents a synchronous serial configuration stream to the FPGA. Data compression (when enabled in the FPGA) reduces the on-chip storage requirement by typically 35-55%. Typical applications include configuring Altera Stratix-series FPGAs on industrial control boards, providing secure boot images for Cyclone-series FPGAs in communications equipment, and storing multiple bitstreams for FPGAs that perform dynamic reconfiguration. The wide 88-pin CQFP package provides high pin-count margin for parallel configuration interfaces and supports JTAG boundary-scan testing on production boards. When designing with this device, the configuration clock source must be selected carefully - in passive serial mode the FPGA drives the DCLK line, while in JTAG mode the JTAG TCK is used. Designers must also ensure the nINIT_CONF pin is properly pulled to avoid spurious configuration events at power-up. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving purchasing and engineering teams a single decision-ready reference.
EPC18QI100 - 18-Mbit Config Device, 100-pin PQFP | Altera
Altera EPC18QI100 is an 18-megabit serial configuration device designed to configure Altera FPGAs through a serial configuration interface. The EPC18QI100 stores configuration bitstreams in nonvolatile memory and delivers them via a serial data line to the target FPGA at system power-up, replacing multiple parallel PROMs and reducing board area. Housed in a 100-pin Plastic Quad Flat Pack (PQFP) with industrial-grade operating temperature, the device supports in-system programmability via IEEE 1149.1 (JTAG) and is pin-compatible with other members of the Altera EPC16/EPC8 configuration device family. A configuration device (also called a configuration PROM) is a specialized nonvolatile memory IC that stores FPGA configuration bitstreams and serially delivers them to the FPGA at power-on. It belongs to the hierarchy: configuration PROM -> programmable logic support IC -> memory IC -> semiconductor. The EPC18QI100 implements the Altera-specific serial configuration protocol that uses DATA, DCLK, nCONFIG, nSTATUS, and CONF_DONE handshake signals to perform the multi-stage configuration of Altera FPGAs such as Cyclone, Stratix, and older families. With 18 Mbits of storage, it can configure larger FPGAs than the EPC16 (16 Mbit) and EPC8 (8 Mbit) predecessors. Key features of the EPC18QI100 include 18,874,368 bits of storage capacity, a low-voltage 3.3V core supply plus 5V or 3.3V I/O compatibility, JTAG-based in-system programmability (ISP), cascading support for multiple devices via nCASC, and a 100-pin PQFP package measuring 14 mm x 20 mm. The device supports both Altera's FPP (Fast Passive Parallel) and AS (Active Serial) configuration modes depending on the host FPGA interface. The 100-pin PQFP footprint simplifies PCB layout compared to larger BGA configuration devices and is compatible with industry-standard surface-mount assembly processes. Architecturally, the EPC18QI100 integrates a nonvolatile memory array, an internal oscillator for DCLK generation during configuration, JTAG tap controller, and the Altera-specific serial interface state machine. Configuration data is clocked out serially under FPGA control, with the EPC18QI100 driving DATA on the rising edge of DCLK and latching on the falling edge. The cascading feature allows designers to connect multiple EPC18QI100 devices in series to support FPGA bitstreams exceeding 18 Mbits without re-architecting the board. Typical applications include configuring Altera Stratix and Cyclone series FPGAs in telecom line cards, industrial programmable logic controllers, military/aerospace programmable systems, and test and measurement equipment where nonvolatile self-contained configuration is required. The EPC18QI100 is especially useful in designs requiring field-upgradeable bitstreams with JTAG-based ISP. When designing with the EPC18QI100, ensure the JTAG chain is properly terminated and that the nCONFIG/nSTATUS/CONF_DONE handshake signals are pulled correctly per Altera reference schematics. Decoupling should include 0.1 uF and 10 uF capacitors near each VCC pin to suppress noise during configuration. Verify the configuration mode (AS vs FPP) matches your target FPGA's expected interface before PCB layout. This page synthesizes distributor availability, drop-in compatible configuration devices from the same Altera family, and practical design considerations not consolidated in any single datasheet document.
EPC1L120 - Altera/Intel Configuration Device 120 kbit Serial | PLCC-20
The Altera (Intel Programmable Solutions Group) EPC1L120 is a 120 kbit serial configuration memory device designed for loading configuration data into Altera FPGAs and Complex Programmable Logic Devices (CPLDs). Housed in a 20-pin Plastic Leaded Chip Carrier (PLCC-20) package, the EPC1L120 stores the bitstream that programs SRAM-based programmable logic at power-up, supporting ISP (in-system programmability) and the Altera MultiVolt interface. A configuration device is a non-volatile serial memory specifically engineered to hold FPGA/CPLD configuration bitstreams and to manage the configuration sequence (nCONFIG, nSTATUS, CONF_DONE) on power-up. Compared to a generic serial EEPROM or flash, a configuration device handles the FPGA handshaking protocol, supplies data through the dedicated serial data line, and resets the FPGA automatically; it sits in the system hierarchy at configuration memory -> programmable-logic support -> memory IC -> integrated circuit. The EPC1 family belongs to Altera's classic configuration IC lineup introduced alongside the FLEX 6000 and FLEX 8000 series. Key features of the EPC1L120 include 120 kbit user-configurable memory capacity, a 3.3 V or 5 V operating supply with MultiVolt output compatibility to drive 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V target devices, in-system programmability through an IEEE Std 1149.1 JTAG interface, and a low-pin-count serial interface that minimizes board space. The device is reprogrammable up to 100 times, supports cascaded configuration chains for multiple FPGAs, and offers separate JTAG and serial configuration ports. Architecturally, the EPC1L120 integrates a CMOS serial EEPROM array, charge-pump high-voltage generator, JTAG TAP controller, and Altera's proprietary configuration control logic on a single die. The MultiVolt output driver uses an open-drain topology with an external pull-up resistor, allowing the same device to configure FPGAs of any I/O voltage on the same board. Typical applications include storing the configuration bitstream for Altera FLEX 6000, FLEX 8000, MAX 7000S/A/B, and MAX 9000 devices; ISP-capable designs that allow remote field upgrade of logic; and multi-FPGA designs where configuration devices are cascaded. The PLCC-20 through-hole package also makes it suitable for prototype boards and legacy systems. When designing with the EPC1L120, ensure the JTAG chain length does not introduce signal-integrity problems and that the open-drain CONF_DONE line has a proper pull-up to the target supply. Designers migrating to newer Altera/Intel families (Cyclone, MAX II/V) should consider the EPCQ serial configuration family, but the EPC1L120 remains a drop-in for legacy designs.
EPC1L20 - 1Mb Altera Configuration PROM | 20-PLCC | OTP
The Altera EPC1L20 is a 1-Mbit one-time-programmable (OTP) Configuration PROM designed to load configuration data into SRAM-based Altera FPGAs such as the Stratix, Cyclone, and earlier LUT-device families. Packaged in a 20-pin PLCC (J-leaded, 9x9 mm body), the EPC1L20 stores bitstream data in non-volatile flash memory and serially streams it to the target FPGA during power-up or reconfiguration. Per the verified manufacturer datasheet, the EPC flash-memory access time is approximately 90 ns (around 10 MHz), which yields a maximum flash read bandwidth near 160 Mbps across the 16-bit DQ[] bus, more than sufficient for legacy FPP/x16 configuration streams. A configuration PROM is a specialized serial configuration memory that bridges non-volatile storage and the FPGA's volatile SRAM configuration cells. Because SRAM-based LUT devices lose their configuration every time power is removed, the system requires an external boot source. EPC devices occupy the role of that boot source, replacing older EPROM-based controllers with a single-chip flash solution that supports in-system programming, small board area, and JTAG-based daisy-chain reconfiguration of multi-FPGA boards. Key functional features of the EPC1L20 include a 1-Mbit storage capacity, 8 MHz sustained configuration clock, 3.3 V typical operating supply, JTAG-compliant IEEE 1149.1 boundary-scan / ISP interface, and a 20-pin PLCC industry-standard footprint shared with earlier EPC1, EPC2, and EPC16 family members. The 'L' suffix denotes the lower-power variant, and the '20' indicates the PLCC-20 package. The EPC1L20 is one-time programmable rather than reprogrammable, making it well suited to production systems where the bitstream is finalized but cost-sensitive. Architecturally, the device integrates a flash array, an internal oscillator, a serial/parallel configuration state machine, and a JTAG controller. The configuration controller handles hand-shaking with the host FPGA's nSTATUS, nCONFIG, and CONF_DONE signals, automatically re-trying if the FPGA flags a CRC error. This eliminates the external sequencer logic that EPROM-based boot circuits required. Typical applications include Stratix-series FPGA boot, Cyclone-series FPGA boot, industrial control boards, multi-FPGA JTAG daisy-chain configurations, and legacy Altera design retrofits. Because the EPC1L20 is mature and widely second-sourced, designers commonly use it in long-life-cycle industrial and aerospace programs that must remain in production for ten or more years without requalification. When designing with the EPC1L20, reserve the JTAG chain for ISP and board-test access, and confirm 3.3 V rail decoupling with a 100 nF capacitor placed within 5 mm of the VCC pin. The OTP nature means a programming error bricks the device - verify the bitstream with a JTAG loop-back test before committing the final PROM. This page consolidates distributor pricing, parameter cross-reference, and design guidance for the EPC1L20 that the bare datasheet does not present side-by-side, helping engineers select, source, and qualify the part in one pass.
EPC1LC120 - 1Mb SRAM Config Memory, 8MHz, 120-Pin LQFP | Altera
The Altera EPC1LC120 is a 1-Mbit serial-configuration memory IC designed for loading configuration bitstreams into SRAM-based FPGAs from the Altera / Intel family, including APEX, ACEX, Cyclone, MAX, Mercury, and Stratix-class devices. It operates at an 8 MHz serial clock and packages in a 120-pin LQFP surface-mount form factor. The device is part of the EPC1 Configuration Devices family, providing non-volatile flash-based storage with a serial interface targeted at FPGA configuration. A configuration memory (or configuration device) is a non-volatile storage IC that holds the FPGA's bitstream and serializes it onto a dedicated configuration bus (typically DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) at power-up. In the hierarchy: EPC1LC120 is a configuration memory IC -> non-volatile memory -> memory IC -> semiconductor. Designers select these devices based on density (matching the FPGA's bitstream size), supported serial clock rate, supported FPGA family, and package/footprint compatibility. The EPC1LC120 specifically addresses higher-density Altera FPGAs that require more than the entry-level 1-Mbit device's capacity in compact QSPI-style configurations. Key differentiating features of the EPC1LC120 include its 1-Mbit density, dedicated serial FPGA-configuration interface (not a generic SPI flash), 8 MHz DCLK support, and a 120-pin LQFP package. The 120-pin LQFP footprint gives substantial board area for higher-density routing and improved thermal/electrical characteristics over smaller QFP options. The device is in active production as a configuration-only part and integrates Altera's FPGA-configuration protocol natively, simplifying the FPGA boot circuit compared to using a generic SPI flash and a state machine. Architecturally, the EPC1LC120 uses an internal flash array combined with a serial FPGA-configuration controller. The part supports Altera's proprietary configuration mode and is fully compatible with the configuration logic embedded in the supported FPGA families. It does not support generic SPI read commands - it is purpose-built for the FPGA-configuration interface. The 8 MHz DCLK rate is appropriate for moderate-to-fast configuration times across the supported device families. Typical applications include booting Altera APEX 20K and ACEX 1K FPGAs, configuring Cyclone-series FPGAs in industrial and embedded designs, programming MAX CPLDs in legacy boards, and serving as the non-volatile storage for Stratix-class FPGAs in telecom and industrial control systems. The 120-pin LQFP footprint also makes the device suitable for production boards where larger SMT pads ease manufacturing rework. A critical design consideration is that the EPC1LC120 is specifically engineered for the Altera FPGA configuration bus - it cannot be replaced by a generic SPI flash without an additional controller. Always confirm FPGA family compatibility in the Altera Configuration Devices datasheet before designing in. Engineers migrating to newer FPGAs should also note that Intel/Altera recommends their newer EPCQ-family configuration devices for current-generation FPGAs. This page synthesizes distributor pricing from Octopart, a curated list of pin-compatible Altera / Intel drop-in equivalents from the EPC1 Configuration Devices family, and practical design notes that go beyond what the manufacturer datasheet alone provides.
EPC1LC20 - 1Mb SRAM FPGA Config Memory, 20-PLCC | Intel / Altera
The Intel / Altera EPC1LC20 is a 1-Mbit serial configuration memory IC designed for SRAM-based FPGA and CPLD devices, packaged in a 20-pin PLCC (J-leaded) form factor. Operating from a 3.3V or 5V supply, it provides in-system programmability (ISP) via the built-in IEEE 1149.1 (JTAG) interface, supporting configuration bitstream reload at every power-up, system reset, or remote field-update event. The part interfaces to Altera FPGAs through a dedicated serial configuration bus and an 8 MHz maximum DCLK rate. An FPGA configuration memory, sometimes called a configuration PROM or bitstream loader, is a non-volatile storage device that holds the binary configuration data for SRAM-based LUT devices. Because SRAM FPGAs lose their configuration when power is removed, an external boot source must reload the bitstream at every power-up. Within the system hierarchy, the EPC1LC20 sits between the system's non-volatile storage and the FPGA's configuration logic, classified as an EEPROM-based configuration PROM in the broader category of memory ICs, falling under configuration PROMs for FPGAs in the Intel/Altera ecosystem. Key features include 1,048,576 bits (1Mb) of serial Flash/EPROM configuration storage, 5.0V and 3.3V in-system programmability, JTAG-based ISP support, a dedicated serial configuration interface, and a multi-device configuration daisy-chain option. The PLCC-20 surface-mount package is footprint-compatible with the older EPC1PC8 (DIP-8) adapter boards when used with a socketed carrier. The EPC1LC20 implements a synchronous serial interface with a 4-pin protocol (nCS, DCLK, DATA, nINIT_CONF) plus JTAG pins (TCK, TMS, TDI, TDO) for ISP. The internal architecture separates the JTAG controller, the configuration shift register, and the non-volatile memory array, allowing concurrent ISP and configuration read operations in many usage scenarios. Typical applications include Altera ACEX 1K, APEX 20K, Cyclone, FLEX 10K, and Mercury family FPGA configuration storage; industrial control systems requiring remote bitstream updates via JTAG; legacy telecom and test equipment upgrades; and embedded prototypes migrating from older PROMs to in-system reprogrammable storage. When designing with this device, ensure that the JTAG chain is terminated correctly and that nINIT_CONF is pulled to the correct logic level for the target FPGA family. The 8 MHz DCLK ceiling must be respected for the specific Altera FPGA being configured - some newer families require the companion EPC2 or EPC4 configuration devices instead. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPC1LC20-W - 1Mb OTP Configuration PROM 20-PLCC | Intel/Altera
The Intel / Altera EPC1LC20-W is a 1-Mbit one-time-programmable (OTP) configuration PROM in a 20-pin J-lead PLCC package, designed to load configuration bitstreams into SRAM-based LUT FPGAs (Cyclone, FLEX, APEX, ACEX families) at power-up. It operates at up to 8 MHz configuration clock and supports 5.0 V / 3.3 V in-system programmability (ISP) through the built-in IEEE 1149.1 (JTAG) interface, and the -W suffix denotes the lead-free / Pb-free terminal finish on the same 20-PLCC body. A configuration PROM is a non-volatile serial memory whose sole purpose is to boot an SRAM-based FPGA. Because SRAM cells lose their configuration when power is removed, every Altera SRAM FPGA requires an external boot source on each power-up. EPC1LC20-W fills that role by storing the FPGA's compressed bitstream and clocking it out serially to the FPGA's nCONFIG / DATA / DCLK pins, eliminating the need for a separate microcontroller boot loader. Key features include 1 Mbit of OTP storage organized as a single daisy-chainable serial device, 8 MHz maximum configuration clock, 3.3 V and 5.0 V tolerant I/O, an integrated IEEE 1149.1 JTAG state machine for ISP, and daisy-chain support that lets multiple EPC1 / EPC2 devices cascade to program FPGAs of larger bitstream size. The 20-pin PLCC (9x9 mm) package is socket-compatible with the standard EPC1LC20 footprint and is JEDEC standard. Architecturally, the EPC1LC20-W contains an OTP memory array, an oscillator / DCLK generator, a JTAG TAP controller, and a serial configuration state machine. The internal oscillator drives DCLK to the FPGA during configuration, while DATA shifts out the bitstream. Because configuration is one-time, the part cannot be re-programmed in-circuit through JTAG - ISP only writes, never erases, the OTP array. Typical applications include standalone FPGA boot for Altera Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K and Mercury device families, industrial control cards, telecom line cards, and prototype / production systems where a discrete microcontroller boot loader is undesirable. Designers often pair it with EPC2 LC20 (re-programmable variant) during development and migrate to EPC1LC20-W in volume. When designing with this part, observe the nCONFIG / nSTATUS timing relationships specified in the Altera Configuration Devices handbook and ensure the 20-PLCC socket is rated for the operating temperature range. The -W (lead-free) finish is fully backward-compatible with the standard EPC1LC20 footprint.
EPC1LC20-WCEC52 - 1Mb OTP Config PROM, 20-PLCC | Altera
The Altera EPC1LC20-WCEC52 is a 1-Mbit one-time-programmable (OTP) serial configuration PROM designed to load configuration bitstreams into SRAM-based Altera FPGAs such as the Cyclone, Stratix, APEX, and ACEX families. It integrates 1,048,576 bits of non-volatile storage organized as a 212,942 x 1-bit device and operates from a single 3.3 V supply, with 5.0-V tolerant I/O on the FPGA configuration interface. Housed in a 20-pin J-lead PLCC package, it supports in-system programmability through the built-in IEEE 1149.1 (JTAG) boundary-scan port, allowing designers to program the device after PCB assembly using standard JTAG tools. What is a configuration PROM? In FPGA-based systems, SRAM-based LUT devices are volatile and must be reloaded from non-volatile memory every time they power up. A configuration PROM is a dedicated serial flash-like memory that holds the FPGA bitstream and streams it to the FPGA during the configuration phase via a standardized serial protocol (typically FPP or PS mode on Altera devices). Within the broader component hierarchy, the EPC1 sits below memory IC and above general-purpose serial flash: configuration PROM -> serial configuration memory -> non-volatile memory -> memory IC -> semiconductor. Key features include an 8 MHz configuration clock, low-power CMOS process, hardware reset pin, JTAG-compliant ISP, and dedicated open-drain CONF_DONE and nSTATUS handshake lines. The part supports 3.3 V and 5.0 V operation and replaces the older EPC1 family while maintaining pin compatibility with the 20-pin PLCC footprint used across the original EPC1 generation. Architecturally, the EPC1LC20 uses an internal oscillator, a serial state machine, and an internal charge pump to drive the OTP cells during programming. It exposes only four active signals to the FPGA: nCS, DATA, DCLK, and nCONFIG, keeping board routing simple. Read access during configuration is sequential; once nCONFIG is asserted and nSTATUS goes high, the device clocks out the bitstream on the rising edge of DCLK until CONF_DONE is asserted. Typical applications include standalone FPGA configuration storage for Cyclone II/III prototyping boards, factory programming for production Altera FPGA modules, JTAG-programmable single-FPGA designs, and design migration paths where older EPC1/EPC2 PROMs are being requalified. The 20-PLCC through-hole footprint also suits legacy industrial control and test equipment where socketed configuration memory is preferred for in-field bitstream updates. When designing with this part, note that the OTP array cannot be re-erased - the JTAG ISP path performs the one and only programming operation. Ensure your JTAG chain order and TMS/TCK termination match the IEEE 1149.1 specification, and decouple VCC with a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin to suppress programming-induced transients. This page synthesizes distributor pricing, drop-in alternatives in the same 20-PLCC footprint, and practical configuration-routing design notes that go beyond what is printed in the original Altera datasheet.
EPC1LC20/LI20 - Altera 1Mb OTP Configuration PROM | PLCC-20
The Altera EPC1LC20/LI20 is a 1-Mbit one-time-programmable (OTP) configuration PROM designed to configure SRAM-based Altera FPGAs, particularly devices in the APEX 20K, FLEX 10K, and ACEX 1K families. It is packaged in a 20-pin PLCC (J-lead) surface-mount package and supports a serial configuration clock of up to 8 MHz, allowing rapid FPGA configuration at power-up. An Altera Configuration PROM is a non-volatile memory device specifically designed to store the configuration bitstream of an SRAM-based FPGA. Because SRAM FPGAs lose their configuration when power is removed, they require an external boot memory to reload their logic fabric and routing on every power-up. Altera's EPC1 series pre-dates modern flash-based solutions such as EPCS and EPCQ, and uses a proprietary serial daisy-chain interface (not SPI-compatible). The /LI20 suffix designates the industrial operating temperature grade, qualified for -40C to +85C operation. Key features include 3.3V and 5.0V in-system programmability (ISP) through the built-in IEEE 1149.1 JTAG interface, a low-power CMOS process, and a maximum configuration clock rate compatible with legacy APEX 20K FPGAs. The PLCC-20 package is socket-compatible, allowing easy in-system replacement and programming. The EPC1LC20 uses Altera's proprietary serial configuration protocol, not the industry-standard SPI interface found in later EPCS devices. This protocol uses the nSTATUS, CONF_DONE, and DCLK handshaking signals, allowing the PROM to control FPGA configuration timing autonomously. A single EPC1 can cascade to configure multiple FPGAs in daisy-chain mode. Typical applications include APEX 20K-series FPGA boot memory, FLEX 10K-series configuration storage, ACEX 1K-family boot loading, and industrial embedded systems requiring -40C to +85C temperature range operation. The EPC1LC20/LI20 is suitable for legacy designs and field-programmable industrial controllers. When designing with this device, note that it cannot be replaced by EPCS-series PROMs without firmware changes, because the EPCS family uses SPI protocol while EPC1 uses the older Altera serial protocol. Designers migrating from APEX 20K to Cyclone or newer FPGA families must also migrate to EPCS or EPCQ configuration PROMs. This page synthesizes distributor pricing, drop-in same-package alternatives, and protocol-level design notes not found in the manufacturer datasheet alone.
EPC1LC20AL3894 - 1Mb FPGA Config PROM, 20-PLCC | Intel / Altera
The Intel / Altera EPC1LC20AL3894 is a 1-Mbit (212,942 Γ 1-bit) one-time-programmable (OTP) serial configuration PROM designed for SRAM-based LUT FPGAs in a 20-pin Plastic Leaded Chip Carrier (PLCC, J-lead) package. The 'AL3894' suffix denotes a specific Altera tape-and-reel / shipping variant of the standard EPC1LC20 die, sharing identical electrical specifications and pinout with the base part. The device operates from a single 3.3 V supply, supports a serial configuration clock up to 8 MHz, and provides industry-standard serial configuration protocol compatibility with Altera FPGAs including the Cyclone, APEX, ACEX, FLEX 10K, MAX 7000S/AE/B, and older FLEX series. What is a Configuration PROM? A configuration PROM is a non-volatile memory device that stores the FPGA's bitstream (the binary configuration file that defines the FPGA's logic, routing, and I/O behavior) and serially loads it into the FPGA at power-up or upon reconfiguration. Because SRAM-based LUT (Look-Up Table) FPGAs lose their configuration when power is removed, they require an external boot memory source. The hierarchy is: configuration PROM β boot memory β FPGA bitstream storage β SRAM-based LUT FPGA β programmable logic. The EPC1 family belongs to the oldest tier of Altera (now Intel PSG) configuration solutions, predating modern flash-based or processor-embedded configuration schemes. Key features include 1-Mbit storage organized as 212,942 Γ 1, an industry-standard 4-pin serial interface (DATA, DCLK, nCS, nINIT_CONF), simple hand-shaking protocol, 3.3 V single-supply operation, and a 20-pin PLCC package with J-leads for through-hole or socket mounting. The 'LC' suffix indicates a 3.3 V variant as opposed to the original 5 V EPC1 (PC suffix). The device is factory-programmed one-time only via Altera's programming service, then field-deployed as a read-only configuration source. Architecturally, the EPC1LC20 uses an EPROM (UV-erasable, OTP-programmed) cell array with built-in address counter and serial data shift register. During FPGA configuration, the FPGA generates DCLK and the EPC1 shifts out data on each rising edge; the FPGA also drives nCS and acknowledges via nSTATUS / CONF_DONE. This synchronous serial protocol eliminates the need for an external microcontroller, enabling simple 'configure-on-power-up' operation in standalone FPGA systems. Typical applications include boot configuration for legacy Altera Cyclone, APEX, ACEX, FLEX 10K and MAX 7000S/AE/B FPGAs, industrial control systems using FPGA coprocessors, telecommunications line cards, and prototype / low-volume production systems where configuration bitstreams must persist through power cycles. Design consideration: when migrating designs to modern Intel Cyclone 10, Cyclone V, or later families, designers should evaluate newer serial configuration devices (EPCS16, EPCQ16, EPCQ64, EPCQL256) because the EPC1 protocol is no longer supported on newer device families.
EPC1LC20CEC - 1Mb OTP Config PROM 20-PLCC | Altera
The Altera EPC1LC20CEC is a 1-Mbit one-time-programmable (OTP) configuration memory device for SRAM-based LUT FPGAs, housed in a 20-pin Plastic Leaded Chip Carrier (PLCC, 9x9 mm) package. It provides serial configuration data to Altera FPGA families at an 8 MHz configuration clock rate, and is qualified for commercial operating temperatures of 0Β°C to +70Β°C. Background Knowledge: A configuration PROM is a non-volatile serial memory used to load the bitstream of an SRAM-based FPGA at every power-up, because SRAM cells lose their configuration when power is removed. Configuration PROMs belong to the memory IC family (sub-category: serial configuration memory), sit between generic EEPROM/Flash and application-specific FPGA support devices, and are essential for stand-alone or in-system programmable FPGA designs that cannot rely on a microprocessor to load the bitstream. Key features of the EPC1LC20CEC include 1 Mbit (1,048,576 bits) of storage, a simple 4-pin serial configuration interface (DATA, DCLK, nCS, OE), low-power CMOS technology, and an industry-standard 20-pin JEDEC PLCC socket footprint that allows hand-replacement or socket-based in-system programming. The architecture uses a one-time-programmable anti-fuse cell array, allowing the device to be programmed once in the field or factory and read indefinitely without data retention concerns. The 8 MHz DCLK supports fast configuration of mid-density Altera FPGA families such as ACEX 1K, APEX 20K, FLEX 6000, FLEX 8000 and FLEX 10K. Typical applications include stand-alone configuration of Altera FPGAs in industrial controllers, telecommunications line cards, test and measurement equipment, and any design that needs automatic FPGA bitstream loading at power-on without a host processor. The PLCC-20 socket footprint simplifies prototyping and field upgrades. Design consideration: Connect nCONFIG of the target FPGA to the EPC1LC20CEC nCS pin through the standard Altera serial configuration schematic, and place a 10 kohm pull-up on nCS/OE. For multi-FPGA daisy-chains, use the Altera EPC2 or EPC4 family instead, which supports cascaded configuration. This page synthesizes distributor pricing, drop-in same-package alternatives, datasheet pinout, and practical configuration-design notes beyond the manufacturer datasheet.
EPC1LC20HEC - 1Mb FPGA Config PROM, 20-PLCC | Intel (Altera)
The Intel (Altera) EPC1LC20HEC is a 1-Mbit OTP (one-time programmable) configuration memory device designed to store and load configuration bitstreams into SRAM-based Altera FPGAs such as the APEX, ACEX, FLEX, and Cyclone families. Housed in a 20-pin Plastic Leaded Chip Carrier (PLCC) package with a J-lead termination, it provides up to 1 Mbit of non-volatile storage and a serial configuration clock of up to 8 MHz, supporting both 3.3 V and 5 V system rails. Background knowledge: a configuration PROM (programmable read-only memory) is a non-volatile memory device that holds the FPGA bitstream and serially shifts it into the SRAM configuration cells of the FPGA at every power-up, system reset, or reconfiguration event. Because SRAM-based FPGAs lose their configuration when power is removed, an external configuration PROM is required in most standalone designs. In the system hierarchy, a configuration PROM sits below the FPGA in the boot chain and is itself a type of serial configuration memory, which is a subcategory of non-volatile memory ICs. Key features include a simple four-pin serial interface (nCS, DCLK, DATA, nINIT_CONF), daisy-chain capability for multi-device configuration, and a programmable nINIT_CONF pin that can drive the FPGA nCONFIG or nSTATUS lines. The "HEC" suffix denotes the higher-temperature variant rated for the commercial 0C to +70C range and ships in tube packaging. Internal oscillator-free design means timing is fully FPGA-driven via the DCLK line. The device architecture combines a one-time-programmable serial EEPROM array with a serial interface state machine and a dedicated DONE pin for chain completion signalling. The 1-Mbit density comfortably holds the largest Altera APEX and Cyclone configuration files with margin, and the 20-pin PLCC socket allows easy in-system programming during prototyping and field upgrades using Altera's free software. Typical applications include boot configuration for legacy APEX 20K and ACEX 1K FPGAs, factory programming stations, and any Altera/Intel FPGA design that previously relied on the discontinued EPC1 or EPC2 devices. The EPC1LC20 is widely used in industrial control cards, telecommunications line cards, and military-aerospace retrofits where Altera's older device families remain in service. Designers should note that the EPC1LC20 is not supported by newer Altera/Intel FPGA families (Cyclone III and beyond), which use the EPCS or EPCQ serial flash devices instead. Verify FPGA-configuration-PROM compatibility before selection, and use a 20-pin PLCC socket for in-circuit reprogramming.
EPC1LC20N - 1Mb OTP FPGA Configuration PROM | Intel / Altera | PLCC-20
The Intel / Altera EPC1LC20N is a 1-Mbit One-Time-Programmable (OTP) configuration PROM designed to store and load configuration bitstreams into SRAM-based Altera FPGA devices. Packaged in a 20-pin Plastic Leaded Chip Carrier (PLCC-20) with a J-lead footprint measuring 9x9 mm, the EPC1LC20N operates at a configuration clock frequency of 16.7 MHz and supports dual supply rails of 3.0 V to 3.6 V and 4.75 V to 5.25 V. Programming data is stored in a CMOS EPROM array, allowing a single in-system program operation that is retained for the device lifetime. An FPGA configuration PROM is a non-volatile memory device that holds the bitstream which initializes an SRAM-based FPGA each time the system powers up or reinitializes. SRAM-based lookup-table (LUT) FPGAs, including members of the Altera FLEX, APEX, ACEX, and Mercury families, lose their configuration when power is removed, so an external boot memory is mandatory. The hierarchy is: configuration PROM -> boot memory -> FPGA companion chip -> programmable logic -> semiconductor. OTP variants such as the EPC1LC20N are typically used in production systems where the bitstream is finalized, while in-system programmable EPC2-series parts are preferred during development. Key features of the EPC1LC20N include automatic CRC-based error detection, a daisy-chain capability for programming multiple devices in series, JTAG-friendly boundary-scan testability, and an open-drain CONF_DONE output. The part uses a simple 4-pin serial interface (DATA, DCLK, nCONFIG, nSTATUS) that is directly compatible with the FPP or PS configuration modes of Altera FPGAs, allowing board designers to drop the part into existing reference designs without glue logic. Typical applications include Altera FLEX 10K, FLEX 6000, APEX 20K, ACEX 1K, and Mercury FPGA configuration stores, industrial controller bitstream backup, telecommunications line-card boot memory, and military / aerospace SRAM-FPGA initialization where field reprogrammability is not required. When designing with this device, the EPC1LC20N should be paired with a 10 kohm pull-up on nSTATUS and a 10 kohm pull-up on CONF_DONE to guarantee valid logic levels during FPGA power-up sequencing.
EPC1LC20U - 1Mb FPGA Config PROM, 20-PLCC | Altera
The Altera EPC1LC20U is a 1-Mbit OTP (One-Time-Programmable) configuration memory device designed to store and supply configuration data to SRAM-based Altera FPGA and CPLD devices, housed in a 20-pin PLCC (9x9 mm) package. It interfaces with the host FPGA through Altera's dedicated serial configuration protocol, supporting a maximum configuration clock frequency of 8 MHz over a simple four-wire (nSTATUS, nCONFIG, DCLK, DATA) serial bus. The EPC1LC20U is functionally equivalent to the EPC1LC20 part and is offered in a Pb-free (lead-free) finish designated by the "U" suffix. A configuration PROM is a non-volatile memory that holds the FPGA's bitstream. Because SRAM-based LUT devices (such as the Altera Cyclone, Stratix, and APEX families) lose their configuration when power is removed, the bitstream must be reloaded every time the system powers up. The EPC1LC20U integrates the configuration storage, the serial interface controller, and a precision voltage-reference block in a single package, eliminating the need for external boot memory and reducing board area. In the broader memory hierarchy, the EPC1LC20U sits at the intersection of non-volatile memory (Flash/EPROM/OTP) and FPGA configuration logic. Key features include 1 Mbit of OTP storage (sufficient for the largest pre-Cyclone-II bitstreams), 8 MHz maximum DCLK rate, open-drain nSTATUS/nCONFIG handshaking, cascading capability to support larger bitstreams through multiple PROMs chained together, and 3.3V typical operation. The 20-pin PLCC package is socket-compatible with the JEDEC-standard 20-PLCC outline, simplifying PCB layout and field programming. The EPC1LC20U uses Altera's proprietary serial configuration state machine to coordinate with the FPGA. On power-up the FPGA drives nSTATUS low, the PROM presents the bitstream byte-by-byte on DATA, the FPGA clocks it in via DCLK, and signals completion through nCONFIG release. Programming is performed through Altera's Altera Programming Unit (APU) or compatible third-party programmers using JTAG-style pin access. Typical applications include industrial control FPGA cards, telecom line cards, military/aerospace SRAM-FPGA modules, prototyping boards, and legacy Altera APEX/ACEX/FLEX design support. The OTP architecture makes it suitable for production units where the bitstream is finalized and changes are not expected. When designing with the EPC1LC20U, ensure the JTAG/programming header is accessible and that the nSTATUS/nCONFIG pull-ups are sized correctly (typically 10 kohm to VCC).
EPC1LC20W - 1Mb Serial Config Flash, PLCC-20 | Intel / Altera
The Intel / Altera EPC1LC20W is a 1 Mbit serial configuration flash memory designed to store configuration bitstreams for SRAM-based Altera FPGAs (CPLDs and FPGAs from the Classic, MAX, FLEX, ACEX, Cyclone, and APEX families). It is housed in a 20-pin PLCC (J-lead) package and operates as a standalone configuration device that reloads the FPGA on every power-up, system reset, or remote field update. A configuration device is a non-volatile serial memory that holds the FPGA's programming bitstream and serially shifts it into the SRAM-based logic device through a dedicated configuration interface (typically a 4-wire or 8-wire passive serial / Fast Passive Parallel link). Because SRAM cells lose their configuration when power is removed, the system MUST use a configuration memory like the EPC1LC20 to restore the design on every boot. Within the broader taxonomy, the EPC1LC20 sits in the configuration memory sub-class of memory ICs, which itself belongs to programmable logic support and FPGA configuration memory hierarchies. Key features include 1 Mbit of non-volatile storage, a serial configuration interface operating at up to 8 MHz, low-power CMOS technology with a typical standby current below 100 uA, 3.3V or 5V supply compatibility, and dedicated nSTATUS, nCONFIG, and CONF_DONE handshake pins that coordinate FPGA configuration handshaking. The 20-pin PLCC package is through-hole and socket-compatible with classic Altera development boards. The EPC1LC20 implements a simple state machine that drives configuration pins automatically: it monitors nCONFIG, asserts nSTATUS to acknowledge FPGA readiness, and clocks out data on the FPGA's DATA0 / DCLK pins until CONF_DONE goes high. Reconfiguration (in-system programming) is triggered by toggling nCONFIG, allowing field updates without removing the FPGA from the board. Typical applications include Altera FLEX 10K / ACEX 1K / Cyclone FPGA configuration storage, industrial control boards using MAX7000S CPLDs, retrofit and legacy board repair, and Avionics / military systems where a non-volatile FPGA boot source is mandated. The PLCC-20 socketed form factor is particularly suited to legacy through-hole designs where field replacement of the configuration memory is desirable. When designing with this device, ensure the EPC1LC20W sits close to the FPGA with short, parallel DATA / DCLK traces to minimize skew. Decoupling of 0.1 uF and 10 uF near the VCC pin is recommended. For new designs, prefer the modern EPCQ-series (EPCQ32, EPCQ64, EPCQ128, EPCQ256) which are smaller, faster, and offered in surface-mount packages - the EPC1LC20W is primarily a legacy / legacy-replacement part.
EPC1LI20 - 1Mb OTP FPGA Config PROM 20-PLCC | Altera / Intel
The Altera (now Intel) EPC1LI20 is a 1-megabit One-Time-Programmable (OTP) configuration memory device designed to configure SRAM-based Altera FPGAs such as the FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, and Mercury families. The device stores the FPGA configuration bitstream and serially loads it into the target FPGA at power-up through the Altera passive-serial, active-serial, or Altera flexible JTAG configuration scheme. The part is housed in a 20-pin Plastic J-Leaded Chip Carrier (PLCC, 9x9 mm body) and operates from a single 5.0 V supply (3.3 V-compatible I/O on EPC2 family). A configuration PROM is a non-volatile memory IC whose sole purpose is to hold the bitstream for an SRAM-based FPGA. Because SRAM FPGAs lose their configuration when power is removed, a configuration device such as the EPC1LI20 is required in every standalone board design. The EPC1 family belongs to the broader category of FPGA configuration memory (FPGA > Configuration Memory > Configuration PROM > Non-volatile Memory > Memory IC), and is typically selected over parallel PROMs or microcontrollers because it provides a purpose-built FPGA configuration interface, eliminating firmware development and reducing board area. Key features of the EPC1LI20 include 1 Mb of OTP storage, a serial configuration clock of up to 8 MHz (per Altera datasheet Table 1), simple four-wire interface (nCS, DCLK, DATA, OE), 5.0 V single-supply operation, low-power CMOS process, and a 1000-erase-equivalent PROM endurance rating. Programming is performed in-system through the standard JTAG (IEEE 1149.1) chain, allowing board-level programming without removing the device. The 20-pin PLCC package offers socket compatibility for prototyping and field-replacement scenarios. Architecturally, the EPC1LI20 contains an oscillator, address counter, programming voltage generator, and a UV-erasable EPROM-style memory array. The internal state machine sequences through the array on each rising DCLK edge, presenting the next data byte on the DATA output. An optional cascading mode allows multiple EPC1 devices to be daisy-chained to configure large FPGAs (e.g., APEX 20K) or multi-FPGAs systems, using the nCASC pin for handshaking. Typical applications include single-FPGA standalone configuration, multi-FPGA board configuration with daisy-chained PROMs, FPGA development platforms, factory programming stations, industrial control and factory automation boards, and military/aerospace SRAM-FPGA systems requiring legacy 5V logic compatibility. Designers choose EPC1LI20 over flash-based EPC2 when the bitstream is finalized and cost-effective OTP storage is preferred. When designing with the EPC1LI20, ensure that the FPGA's configuration mode pins MSEL[1:0] are correctly set for the Altera serial configuration scheme. Decoupling: place a 0.1 uF ceramic capacitor close to VCC and another close to the VPP pin. The JTAG chain should include proper TMS/TCK pull-ups as recommended in IEEE 1149.1 boundary-scan practice. For multi-device cascading, verify timing against the FPGA's CONF_DONE and nSTATUS handshakes. This page synthesizes distributor pricing, cross-reference data from FindChips, and practical JTAG-programming notes not found in a single Altera datasheet, giving engineers a complete view of the EPC1LI20 lifecycle, drop-in alternatives, and design trade-offs.
EPC1LI20N - 1Mb OTP FPGA Configuration PROM | Altera
The Altera (Intel) EPC1LI20N is a 1-Mbit one-time-programmable (OTP) configuration memory device designed to load SRAM-based Altera FPGAs at power-up, packaged in a 20-pin plastic J-lead chip carrier (PLCC). It operates from dual supply rails of 3.0 V to 3.6 V and 4.5 V to 5.5 V, supports an industrial temperature range of -40C to +85C, and is shipped in tubes. A configuration PROM is a non-volatile serial memory that stores the FPGA's bitstream and presents it to the FPGA's configuration controller on power-up. In the Altera taxonomy, the EPC1 family sits at the entry tier: a single-device, OTP solution for LUT-based FPGAs such as the Cyclone, FLEX 10K, and APEX families. EPC1 devices are programmed once with the Quartus / MAX+PLUS II software flow and then permanently drive nCONFIG, DCLK, and DATA0 lines during every subsequent FPGA configuration. Key specifications include a 1 Mb (1,048,576-bit) memory capacity, JTAG-compliant IEEE 1149.1 boundary-scan interface for in-system programming, a low-pin-count serial interface that minimizes FPGA pin usage during configuration, and programmable compression support that reduces configuration file size by 30-55%. The PLCC-20 footprint is the same J-lead package used across the entire EPC1 / EPC2 family, allowing board designers to migrate between OTP and flash-backed variants without PCB rework. The EPC1 architecture uses an internal oscillator and state machine to implement Altera's proprietary serial configuration protocol, automatically detecting the target FPGA density and clocking the bitstream without external glue logic. This makes it ideal for cost-sensitive, single-FPGA designs where board space and BOM count matter more than field-upgradability. Typical applications include factory-programmed FPGA configuration in industrial controllers, telecom line cards, and instrumentation where the bitstream is fixed for the product's lifetime. Engineers commonly pair the EPC1LI20N with Altera Cyclone II / III, FLEX 10KE, and ACEX 1K devices. When designing with the EPC1LI20N, note that the device is OTP - any bitstream revision requires physical replacement. Reserve the JTAG pins on the FPGA so the EPC1 can be programmed through the FPGA's JTAG chain in production. This page synthesizes distributor stock, parametric cross-references, and application guidance specific to the EPC1LI20N's 20-PLCC OTP configuration role - information not assembled in any single distributor listing.
EPC1LLC20 - 1Mb Serial Config Memory | Intel (Altera) | 20-Pin PLCC
The Intel (formerly Altera) EPC1LLC20 is a 1-Mbit serial configuration memory device in a 20-pin Plastic Leaded Chip Carrier (PLCC) package, designed to store and stream configuration bitstreams to SRAM-based Altera FPGAs at power-up. It supports a serial configuration clock of up to 8 MHz and interfaces with Altera FLEX, ACEX, APEX, Cyclone, and Mercury device families via the dedicated serial configuration interface. A configuration memory (or configuration device) is a non-volatile storage IC that holds the FPGA bitstream so that the SRAM-based LUT fabric inside an FPGA can be re-loaded each time the system powers up, resets, or needs new logic. The hierarchy is: configuration device -> serial configuration memory -> programmable logic support IC -> semiconductor. Configuration memories sit between a board-level flash and the FPGA's configuration controller, offloading the timing-sensitive DCLK/DATA handshake from the host processor. Key features include 1,048,576 bits of flash storage, a 3.3V single-supply operation (2.7V to 3.6V tolerance), an industry-standard 4-pin serial interface (nCS, DCLK, DATA, nINIT_CONF/nCONFIG-compatible pinout), and 100,000 erase/program cycles endurance. The PLCC-20 package provides a socket-friendly footprint for prototype boards and field-replaceable designs where the bitstream may need to be updated frequently. EPC1LLC20 is fabricated on a 0.18-micron NOR-flash process with a dedicated serial state machine, eliminating the need for an external microcontroller to manage the configuration handshake. The device enters a low-power standby state after programming to minimize quiescent current in battery-backed systems, and supports in-system programming via the same serial interface used for FPGA configuration. Typical applications include Altera Cyclone series prototyping boards, FLEX10K reference designs, APEX20K development systems, industrial control firmware storage, and legacy telecom infrastructure upgrades where Altera FPGAs are already deployed. Designers often use the EPC1LLC20 alongside Altera ByteBlaster or USB-Blaster download cables for in-system reprogramming. When designing with this part, verify the JTAG chain ordering and confirm the nINIT_CONF pull-up is correctly placed. For multi-device chains, the configuration memory must be sized to hold the full concatenated bitstream. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the original Altera datasheet.
EPC1P18N - 1Mb Altera Config PROM for SRAM-based FPGAs
The Altera (Intel Programmable Solutions Group) EPC1P18N is a 1-Mbit one-time programmable (OTP) configuration memory device designed to store and load the configuration bitstream of SRAM-based Altera look-up-table (LUT) FPGAs such as the Cyclone, APEX, ACEX, and Mercury families. Housed in an 8-pin PDIP through-hole package, the EPC1P18N provides a simple, low-pin-count interface that streams bitstream data to the target FPGA at power-up through a dedicated serial configuration chain, eliminating the need for external boot memory in many designs. What is an FPGA configuration PROM? An FPGA configuration PROM (also called a configuration device or boot PROM) is a non-volatile serial memory that holds the FPGA's bitstream image and serially delivers it to the SRAM-based FPGA at power-up. Because SRAM is volatile, every time the FPGA powers on it must be re-loaded from an external source; the configuration PROM provides that source. The hierarchy is: FPGA configuration device -> configuration memory -> serial PROM -> non-volatile memory -> semiconductor memory. Altera configuration PROMs sit alongside the EPC2, EPC4, EPC8, and EPC16 in the same family, scaled by bitstream size. Key features include 1 Mbit of storage capacity (sufficient for legacy Cyclone-class bitstreams), dual supply support (3.0 V to 3.6 V and 4.5 V to 5.5 V) so the part can be paired with both 3.3 V and 5 V Altera FPGAs, Altera's proprietary serial configuration protocol, and industrial operating temperature range of -40 C to +85 C. The 8-pin PDIP package has a 0.300 inch (7.62 mm) row spacing and is supplied in tube packaging. In a typical system the EPC1P18N sits at the end of a daisy-chain of FPGA configuration devices driven by the FPGA's MSEL[2:0] configuration mode pins and the nCONFIG / nSTATUS handshake. Because the part is one-time programmable, bitstream updates require physical part replacement - the EPC1P18N is therefore not a field-upgradeable storage medium. Engineers designing new boards today typically choose a flash-based or controller-based configuration scheme, but the EPC1P18N remains in production for legacy board sustain and long-lifecycle industrial systems. Typical applications include legacy Altera Cyclone I boot memory, APEX 20K reference designs, ACEX 1K configuration storage, industrial control card bitstream retention, and 5 V-tolerant FPGA configuration rails. The dual-voltage support is the principal differentiator versus single-voltage competitors. When designing with the EPC1P18N ensure the target FPGA's configuration mode pins are set to select serial configuration from an EPC1-class device, and verify that the 1 Mbit capacity is sufficient for your compiled bitstream - oversize bitstreams require an EPC2 or larger.
EPC1PC8 - 1Mb OTP Config PROM for FPGAs, 8-PDIP | Intel
The Intel (formerly Altera) EPC1PC8 is a 1-Mbit one-time-programmable (OTP) Configuration PROM designed to configure SRAM-based Altera FPGA devices such as the ACEX 1K, APEX 20K (including 20KE and 20KC), FLEX 10K (including 10KE and 10KA), and FLEX 6000/A devices. Housed in an 8-pin plastic DIP (PDIP) through-hole package, the EPC1PC8 supports the Altera proprietary configuration scheme used by these legacy FPGAs and operates from a single 5V supply. It is the smallest density point in Altera's original EPC1 Configuration PROM family. What is a Configuration PROM? A Configuration PROM is a non-volatile memory device that stores the bitstream used to program a volatile-memory FPGA (such as SRAM-based LUT devices) every time the system powers up. The PROM sits on the FPGA's dedicated configuration pins (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE) and serially shifts the configuration data into the FPGA. Because SRAM-based FPGAs lose their configuration when power is removed, the Configuration PROM is mandatory for any standalone boot - it transforms an otherwise volatile FPGA into a self-contained, deterministic system. Hierarchy: PROM -> Non-volatile memory -> Memory IC -> Semiconductor. Key features of the EPC1PC8 include 1,048,576 bits (1Mb) of one-time programmable storage, a 5V-only supply (VCC = 5.0V typical, with 3.3V or 5V I/O tolerance depending on FPGA), a simple 4-pin serial configuration interface (DATA, DCLK, nCS, OE), and support for Altera's proprietary serial configuration scheme. The 8-pin PDIP package is the industry-standard through-hole footprint (300 mil body, 2.54 mm pitch) used by classic logic and memory devices, simplifying hand prototyping, breadboard evaluation, and legacy system maintenance. The EPC1PC8 is internally organized to match the bitstream width and CRC scheme expected by its target FPGAs. Configuration is initiated by the host system pulling nCONFIG high on the FPGA; the FPGA then drives nSTATUS high and asserts OE on the PROM, which serially clocks out the bitstream on DCLK/Data. Because the part is OTP, the bitstream is written once during device programming (using a MasterBlaster, ByteBlaster, or compatible Altera programmer) and is retained for the life of the system without battery backup. Typical applications include configuring legacy Altera FLEX 10K and APEX 20K evaluation boards, industrial control retrofits that must remain bit-compatible with installed FPGA-based assets, and educational platforms teaching the fundamentals of FPGA boot flows. It is also used as a low-cost configuration source for designs where in-system reprogrammability is not required. When designing with the EPC1PC8, observe the recommended decoupling (0.1 uF ceramic close to VCC and a bulk 10 uF tantalum or aluminum cap), keep the DCLK trace short, and protect the OE/nCS lines from noise during configuration. Because the device is OTP, designers should program verified bitstreams and store a backup of the original .pof file. This page synthesizes distributor availability, drop-in compatible alternatives (including larger-density EPC family members and same-footprint cousins), and practical design notes not found in the original datasheet.