EP1810GC-35 vs EP1810JC-25 Comparison

Detailed side-by-side comparison of EP1810GC-35 by Altera and EP1810JC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810GC-35 EP1810JC-25
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy NRND
Stock Status In Stock In Stock
Unit Price (USD) $177.12 $6.80
Device Type EPLD (Erasable Programmable Logic Device) —
Logic Family Altera Classic EPLD —
Technology CMOS, UV-erasable EPROM cells CMOS, UV-erasable (windowed ceramic DIP)
Package CPGA-68 (Ceramic Pin Grid Array, 68-pin) 28-pin ceramic DIP (J) with quartz window
Number of Pins 68 —
Propagation Delay (tpd max) 40 ns —
Maximum Inputs 64 —
Maximum Outputs 48 —
Macrocells 16 48
I/O Standard TTL-compatible —
Programming Method UV erasure + EPROM programming —
Operating Temperature [DATA_NEEDED: operating temperature range] -40 °C to 85 °C (industrial, per distributor listings)
Supply Voltage [DATA_NEEDED: VCC range] —
Mounting Type Through Hole Through-hole
RoHS Status Not applicable (legacy ceramic package) [DATA_NEEDED: RoHS compliance status]
Lead-Free Status Not applicable —
Manufacturer (current source) Rochester Electronics (authorized Altera EPLD partner) —
Original Manufacturer Altera Corporation (now Intel FPGA) —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — Altera/Intel Classic EPLD (EP1810 series)
Propagation Delay (tPD) — 25 ns
Maximum Toggle Frequency — [DATA_NEEDED: max fMAX]
Input Lines — 60 (including I/O)
I/O Lines — 48
Dedicated Inputs — 12
External Clock Inputs — 4
Supply Voltage (VCC) — 4.75 V to 5.25 V
Erasure Method — UV light (windowed package)
Lifecycle Status — NRND (Not Recommended for New Designs)

Datasheets & Resources

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