EP1810GC-35 vs EP1810JC-25 比較
詳細な並列比較: EP1810GC-35 メーカー: Altera および EP1810JC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810GC-35 | EP1810JC-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $177.12 | $6.80 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | CMOS, UV-erasable (windowed ceramic DIP) |
| パッケージ | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | 28-pin ceramic DIP (J) with quartz window |
| ピン数 | 68 | — |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40 °C to 85 °C (industrial, per distributor listings) |
| 電源電圧 | [DATA_NEEDED: VCC range] | — |
| 実装タイプ | Through Hole | Through-hole |
| RoHS ステータス | Not applicable (legacy ceramic package) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera/Intel Classic EPLD (EP1810 series) |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Erasure Method | — | UV light (windowed package) |
| ライフサイクル状態 | — | NRND (Not Recommended for New Designs) |