EP1810GC-35 vs EP1810JC-25 비교
다음의 상세 나란히 비교: EP1810GC-35 제조: Altera 및 EP1810JC-25 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810GC-35 | EP1810JC-25 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $177.12 | $6.80 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | CMOS, UV-erasable (windowed ceramic DIP) |
| 패키지 | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | 28-pin ceramic DIP (J) with quartz window |
| 핀 수 | 68 | — |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | -40 °C to 85 °C (industrial, per distributor listings) |
| 공급 전압 | [DATA_NEEDED: VCC range] | — |
| 실장 유형 | Through Hole | Through-hole |
| RoHS 상태 | Not applicable (legacy ceramic package) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera/Intel Classic EPLD (EP1810 series) |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Erasure Method | — | UV light (windowed package) |
| 수명 주기 상태 | — | NRND (Not Recommended for New Designs) |