EP1810GC-35 vs EP1810JI-35 Comparison

Detailed side-by-side comparison of EP1810GC-35 by Altera and EP1810JI-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810GC-35 EP1810JI-35
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $177.12 $18.60
Device Type EPLD (Erasable Programmable Logic Device) —
Logic Family Altera Classic EPLD —
Technology CMOS, UV-erasable EPROM cells —
Package CPGA-68 (Ceramic Pin Grid Array, 68-pin) 28-pin JLCC (J-leaded ceramic, windowed)
Number of Pins 68 —
Propagation Delay (tpd max) 40 ns —
Maximum Inputs 64 —
Maximum Outputs 48 —
Macrocells 16 48
I/O Standard TTL-compatible —
Programming Method UV erasure + EPROM programming —
Operating Temperature [DATA_NEEDED: operating temperature range] -40C to +85C (Industrial)
Supply Voltage [DATA_NEEDED: VCC range] 5 V (typical classic EPLD)
Mounting Type Through Hole Through-Hole (J-lead)
RoHS Status Not applicable (legacy ceramic package) [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC]
Lead-Free Status Not applicable —
Manufacturer (current source) Rochester Electronics (authorized Altera EPLD partner) —
Original Manufacturer Altera Corporation (now Intel FPGA) —
Device Family — Classic EPLD
Logic Array Blocks — 8 LABs of 16 macrocells
Dedicated Inputs — 48
Pin-to-Pin Propagation Delay (tPD) — 35 ns
Speed Grade — -35
Process Technology — CMOS EPROM (UV-erasable)
Programmability — UV-erase, windowed for lab reprogram
MSL Level — [DATA_NEEDED: MSL rating]
Programming Interface — JEDEC fuse file via legacy programmer

Datasheets & Resources

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