EP1810GC-35 vs EP1810JI-35 Comparaison
Comparaison détaillée côte à côte de EP1810GC-35 par Altera et EP1810JI-35 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810GC-35 | EP1810JI-35 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $177,12 | $18,60 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | — |
| Boîtier | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | 28-pin JLCC (J-leaded ceramic, windowed) |
| Nombre de broches | 68 | — |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Tension d'alimentation | [DATA_NEEDED: VCC range] | 5 V (typical classic EPLD) |
| Type de montage | Through Hole | Through-Hole (J-lead) |
| Statut RoHS | Not applicable (legacy ceramic package) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |