EP1810GC-35 vs EP1810JI-35 对比
详细并排对比 EP1810GC-35 出自 Altera 和 EP1810JI-35 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810GC-35 | EP1810JI-35 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $177.12 | $18.60 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | — |
| 封装 | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | 28-pin JLCC (J-leaded ceramic, windowed) |
| 引脚数 | 68 | — |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| 电源电压 | [DATA_NEEDED: VCC range] | 5 V (typical classic EPLD) |
| 安装类型 | Through Hole | Through-Hole (J-lead) |
| RoHS 状态 | Not applicable (legacy ceramic package) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| MSL 等级 | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |