EP1810GC-35AB - Classic EPLD, 48 Macrocells, 35ns | Altera
MPN: EP1810GC-35AB β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
Drop-in alternatives for EP1810GC-35AB β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810GC-35
β Drop-Inβ In Stock
$177.12 / Unit
View Datasheet βEP1810GC-50
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP1810GM-35
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP1810GC-30
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP1810GC-35AB Maximum Ratings & Electrical Characteristics
| Product Family | Classic EPLD |
| Technology | CMOS EPROM |
| Number of Macrocells | 48 |
| Number of Usable Gates | 1200 |
| Maximum Inputs | 64 |
| Maximum Outputs | 48 |
| Number of I/O Pins | 48 |
| Dedicated Input Pins | 12 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Toggle Frequency | 62.5 MHz |
| Supply Voltage (VCC) | 5 V |
| Package Type | Pin Grid Array (PGA), ceramic |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface |
| RoHS Status | unknown |
EP1810GC-35AB pin grid array (pga), ceramic Pin Configuration Guide
Complete pinout information for EP1810GC-35AB (pin grid array (pga), ceramic package) with 12 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1810GC-35AB.
Refer to the datasheet for full pin configuration.
Estimated pin count: 12 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810GC-35AB is suitable for 6 applications: Microprocessor Bus Decoding and Address Mapping, State Machine Implementation in Industrial Control, Legacy Telecom Interface and Glue Logic, Military and Aerospace Avionics Systems, Test and Measurement Equipment Front-End, Replacement of Multiple 74LS/74F TTL Gates.
Microprocessor Bus Decoding and Address Mapping
The EP1810GC-35AB's 48 macrocells and 12 dedicated input pins make it ideally suited for decoding 16-bit microprocessor address buses and generating chip-select signals for memory and peripheral mapping. With a 35 ns tPD, the device comfortably meets the address-to-chip-select timing budgets of 8 MHz to 25 MHz microprocessors (e.g., 8086, 68000, Z80) where the address latch-to-CS window is typically 40-60 ns. The deterministic AND/OR-array delay is preferable to discrete 74LS138/139 decoder trees because it allows late-stage board revisions without trace-by-trace timing re-validation. In legacy industrial PCs and embedded controllers, the EP1810GC-35AB often replaces 4-6 TTL packages, reducing board area and improving noise margin.
Recommended
State Machine Implementation in Industrial Control
The EP1810GC-35AB's 48 flip-flop-equipped macrocells provide ample register capacity for implementing multi-state finite state machines (FSMs) in industrial control and instrumentation equipment. Each macrocell supports registered, combinational, or bidirectional I/O with asynchronous clear and global clock, enabling clean Moore/Mealy state machines with deterministic 35 ns state-transition latency. The ceramic PGA package delivers the thermal headroom required for sealed industrial enclosures operating at elevated ambient temperatures. Designers can encode 16-32 state machines within a single device, with the remaining macrocells dedicated to input conditioning, debouncing, and output latching for relay drivers.
Recommended
Legacy Telecom Interface and Glue Logic
The EP1810GC-35AB is widely deployed in legacy telecom infrastructure (e.g., T1/E1 framers, DSLAM line cards, cross-connect switches) as glue logic between protocol controllers, PHYs, and backplane transceivers. Its 48 I/O pins and 64-input AND/OR array allow it to absorb 4-8 discrete 74F/74AS TTL packages per device, simplifying board layout and reducing propagation-delay skew. The 35 ns tPD is well-matched to the 8.192 MHz PCM frame-clock domain typical of T1/E1 systems. Long-term supply via Rochester Electronics makes the EP1810GC-35AB a viable sustainment solution for telecom carriers required to maintain 20-30 year field-life equipment.
Recommended
Military and Aerospace Avionics Systems
The ceramic PGA package of the EP1810GC-35AB (-GM military-grade variant) supports the extended temperature range (-55C to +125C) and mechanical ruggedness required for military and aerospace applications. The device is used in legacy avionics bus interfaces (e.g., MIL-STD-1553, ARINC 429), radar signal conditioning, and flight-control redundant logic. The EPROM technology provides radiation tolerance for space applications and secure field-programmable configurations for cryptographic equipment. Long-term die-bank inventory at Rochester Electronics ensures continued supply for sustainment programs with 20+ year field-life requirements.
Recommended
Test and Measurement Equipment Front-End
The EP1810GC-35AB's deterministic timing and 48 I/O pins make it useful for digital test equipment, logic analyzers, and protocol analyzers where precise pattern generation, handshaking, and trigger sequencing are required. The 35 ns tPD allows accurate generation of test patterns at frequencies up to 28 MHz, and the 48 macrocells can be partitioned into independent timing generators, pattern sequencers, and handshake state machines. The ceramic PGA package and 5 V VCC also simplify integration with TTL-compatible front-end circuits common in older instrument designs.
Recommended
Replacement of Multiple 74LS/74F TTL Gates
The EP1810GC-35AB is commonly used to consolidate 4-8 packages of 74LS, 74F, 74ALS, or 74AS discrete TTL logic into a single programmable device, reducing PCB area, power consumption, and inventory burden. Each Classic EPLD macrocell can replace a 74LS00 quad NAND, 74LS151 8:1 mux, 74LS153 dual 4:1 mux, or 74LS161 counter when configured appropriately. The 48-macrocell density enables replacement of an entire 74LS244/245/373/374 buffer tree plus decoder logic. Designers benefit from late-stage design changes without board respins, a key advantage over fixed-function TTL.
Recommended
Recommended Products Summary
Engineering reference data for EP1810GC-35AB β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810GC-35 | EP1810GC-30 | EP1810GC-50 | EP1810GM-35 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | PGA (ceramic) | PGA (ceramic) - same | PGA (ceramic) - same | PGA (ceramic) - same | PGA (ceramic) - same |
| Propagation Delay (tPD) | 35 ns | 35 ns | 30 ns | 50 ns | 35 ns |
| Macrocells | 48 | 48 | 48 | 48 | 48 |
| Usable Gates | 1200 | 1200 | 1200 | 1200 | 1200 |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Military (-55C to +125C) |
| Technology | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete (military) |
Key Differentiators
- Same silicon die as EP1810GC-35 with AB suffix revision (vs EP1810GC-35)
- Faster propagation delay available in same package (vs EP1810GC-50)
- Military-grade variant available for harsh environments (vs EP1810GM-35)
Design Notes
The ceramic PGA package requires a through-hole PCB footprint with a 17x17 or 19x19 grid pattern depending on revision. For prototypes and low-volume production, use a machined-pin PGA socket (e.g., 3M Textool or equivalent) to allow UV erasure and reprogramming of the EPROM cells. For production, the device can be soldered directly into plated through-holes, but this permanently commits the programmed logic - ensure 100% design validation before solder-down. Decoupling: place one 0.1 uF ceramic capacitor per VCC pin and one 10 uF tantalum bulk capacitor near each VCC plane to suppress switching noise on the AND/OR array.
The "-35" speed grade suffix indicates 35 ns maximum tPD at 5.0 V VCC and 25 C ambient; at lower VCC (e.g., 4.75 V minimum) and higher temperature (e.g., 70 C commercial max), tPD may degrade by 10-20%. Designers should add 25% timing margin to address-to-chip-select paths. Additionally, the EPROM cell requires a 20-30 minute UV erasure at 12,000 uW/cm2 before reprogramming - ensure quartz-windowed packages are exposed properly. One-time-programmable (OTP) versions without a window require new silicon for each design change.
Although the EP1810GC-35AB is a 5 V CMOS device with TTL-compatible I/O, simultaneous switching of all 48 outputs can inject significant ground bounce on the GND pin and VCC rail. Use a 4-layer PCB with dedicated ground and power planes; avoid socket-based PGA connections for high-speed applications above 20 MHz. For designs exceeding 25 MHz toggle rates, series-damping resistors (22-33 ohm) on each output help dampen transmission-line reflections on traces longer than 50 mm. Estimated: a 48-output simultaneous switching event at 5 V/35 ns produces approximately 1.2 A of dynamic supply current.
Compliance Information
Ceramic PGA package from the Classic EPLD family typically uses Sn/Pb solder balls/leads; lead-free status not confirmed in available web data. RoHS/REACH compliance not documented by Altera for this obsolete family.
