EP1810JC-35 - 48-Macrocell UV EPLD, 35ns, CQCC-68 | Intel / Altera
MPN: EP1810JC-35 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6 | $6.00 |
| 10 | $5.83 | $58.30 |
| 100 | $5.65 | $565.00 |
| 200 | $5.65 | $1,130.00 |
| 500 | $5.48 | $2,740.00 |
Drop-in alternatives for EP1810JC-35 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1810JC-25
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View Datasheet →EP1810GC-35AB
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View Datasheet →EP1810GI-45
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View Datasheet →EP1810JC-35 Maximum Ratings & Electrical Characteristics
| Device Family | Classic EPLD (EP1810) |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | 48 |
| Propagation Delay (tpd) | 35 ns (max) |
| Process Technology | CMOS |
| Supply Voltage (Vcc) | 5 V (nominal) |
| Maximum Supply Voltage | 5.25 V (per distributor listing) |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | 68 |
| Terminal Form | J-Bend |
| Operating Temperature Range | 0°C to 70°C (Commercial) |
| Temperature Grade | Commercial |
| Erasure Method | UV (quartz-windowed ceramic package) |
| RoHS Status | Compliant (per Altera listing) |
| Lead-Free Status | Lead-free (per distributor listing) |
| Mounting Type | Surface Mount (J-Lead) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs |
EP1810JC-35 cqcc-68 (ceramic j-lead chip carrier, qccj) Pin Configuration Guide
Complete pinout information for EP1810JC-35 (cqcc-68 (ceramic j-lead chip carrier, qccj) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1810JC-35.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810JC-35 is suitable for 6 applications: Legacy Telecom Backplane Glue Logic, Industrial Control Card State Machine, 8086/80286 Microprocessor Address Decoder, Bus Arbitration and Interrupt Controller, Avionics Ground-Test Fixture Logic, Legacy Peripheral Adapter Card.
Legacy Telecom Backplane Glue Logic
The EP1810JC-35 is well-suited to legacy telecom backplane glue-logic replacement where 48 macrocells, 35 ns propagation delay, and 5 V CMOS interfaces integrate address decoding, bus arbitration, and interrupt control previously implemented in 74LS/74AS TTL. The 35 ns tpd comfortably meets typical backplane clock periods in the tens of MHz, and the UV-erasable non-volatile configuration enables field re-programmability for protocol updates. The CQCC-68 J-lead ceramic package supports through-hole or socketed assembly typical of telecom line-card designs, and the part's 5 V interface is directly compatible with legacy TTL signaling without level shifters.
Recommended
Industrial Control Card State Machine
The EP1810JC-35 fits industrial control card state-machine integration where deterministic timing and non-volatile configuration are required. Its 48 macrocells accommodate multi-state controllers for motor sequencing, conveyor logic, and sensor-fusion arbitration, while the 35 ns tpd provides predictable timing analysis for safety-critical control loops. The CMOS process technology keeps standby power low for always-on industrial controllers, and the 5 V supply matches the prevailing PLC and sensor-interface voltage rails. UV erasability allows field updates during commissioning, and the commercial 0-70°C range covers most factory-floor environments when paired with sealed enclosures.
Recommended
8086/80286 Microprocessor Address Decoder
The EP1810JC-35 is ideal for 8086/80286-era microprocessor address decoding and wait-state generation. Its 48 macrocells implement complex address maps, chip-select logic, and READY/WAIT-state generators in a single device, replacing multiple 74LS138 / 74LS139 decoders and discrete gates. The 35 ns propagation delay fits the access-time budget of these legacy CPUs at typical 8-10 MHz bus clocks, and the 5 V CMOS interface directly connects to the 8086 address and control bus without buffering. UV-erasable non-volatile configuration simplifies production programming and field servicing.
Recommended
Bus Arbitration and Interrupt Controller
The EP1810JC-35 integrates multi-master bus arbitration and interrupt priority controllers in legacy VMEbus and Multibus systems. Its 48 macrocells encode priority encoders, daisy-chain arbiters, and vector-interrupt logic that previously required 74LS/AS TTL MSI packages, while the 35 ns propagation delay handles arbitration propagation within one bus cycle at moderate clock rates. The device's registered macrocell outputs simplify edge-triggered arbitration protocol implementation, and its 5 V CMOS signaling matches legacy backplane electrical specifications. CQCC-68 packaging supports socketed field-replacement strategies.
Recommended
Avionics Ground-Test Fixture Logic
The EP1810JC-35 supports avionics ground-test fixture and bench-test equipment logic where deterministic timing and field re-programmability are essential. Its 35 ns propagation delay fits MIL-1553 and ARINC 429 test fixtures that operate at moderate data rates, and its 48-macrocell capacity implements pattern generators, protocol monitors, and stimulus-response comparators in one device. The UV-erasable non-volatile configuration enables fixture updates as new aircraft protocols are validated, while the CQCC-68 ceramic package tolerates bench-environment thermal cycling and ESD events better than plastic alternatives.
Recommended
Legacy Peripheral Adapter Card
The EP1810JC-35 is widely deployed in legacy peripheral adapter cards such as SCSI controllers, parallel I/O expanders, and GPIB interface boards. Its 48 macrocells implement command decoders, DMA handshake logic, and protocol-state machines, while the 35 ns tpd matches the timing requirements of these moderate-speed parallel buses. The 5 V CMOS interface is directly compatible with peripheral driver/receiver chips of the era, and the UV-erasable ceramic CQCC-68 package supports OEM qualification cycles with multiple design revisions before OTP production units are committed.
Recommended
Recommended Products Summary
Engineering reference data for EP1810JC-35 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810JC-25 | EP1810GM883B | EP1810GC-35 | EP1810GI-45 | EP1810GM/883B |
|---|---|---|---|---|---|---|
| Package | CQCC-68 (QCCJ, J-Lead) | CQCC-68 (QCCJ, J-Lead) - same | Ceramic PGA equivalent - same die, different package | CQCC-68 (Gull-Wing) - same footprint, different lead form | CQCC-68 (industrial temp) - same | Ceramic PGA equivalent - same die, different package |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Number of Macrocells | 48 | 48 (same) | 48 (same) | 48 (same) | 48 (same) | 48 (same) |
| Propagation Delay (tpd) | 35 ns | 25 ns (~29% faster) | 35 ns (same) | 35 ns (same) | 45 ns (~29% slower) | 35 ns (same) |
| Process Technology | CMOS | CMOS | CMOS | CMOS | CMOS | CMOS |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0°C to +70°C (Commercial) | 0°C to +70°C (Commercial) | -55°C to +125°C (Mil-Std-883B) | 0°C to +70°C (Commercial) | -40°C to +85°C (Industrial) | -55°C to +125°C (Mil-Std-883B) |
| Erasure Method | UV (ceramic window) | UV (ceramic window) | UV (ceramic window, Mil grade) | UV (ceramic window) | UV (industrial temp ceramic) | UV (ceramic window, Mil-Std-883B) |
| RoHS / Lead-Free | Compliant / Lead-free | Compliant / Lead-free | [DATA_NEEDED] | Compliant / Lead-free | [DATA_NEEDED] | [DATA_NEEDED] |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Faster speed grade available in identical CQCC-68 package (vs EP1810JC-25)
- Military temperature range available in same die (vs EP1810GM883B)
- Industrial temperature range variant with extended tolerance (vs EP1810GI-45)
Design Notes
Estimated: confirm propagation-delay budget before substituting a slower speed grade. The EP1810GI-45 offers 45 ns tpd versus the EP1810JC-35's 35 ns, a ~29% slowdown that may violate your timing closure if your design relies on the 35 ns budget margin. Conversely, moving up to the EP1810JC-25 (25 ns tpd) gives 28% timing margin improvement at the same price band. According to Altera, all EP1810 speed grades share identical JTAG programming and functional behavior, so timing verification is the only design risk when swapping grades.
Estimated: the ceramic CQCC-68 J-lead package of the EP1810JC-35 has no exposed thermal pad and is rated for commercial 0-70°C operation. For higher ambient temperatures or higher toggle activity, switch to the EP1810GI-45 industrial-temperature grade (-40°C to +85°C) or the EP1810GM883B Mil-Std-883B variant (-55°C to +125°C). The CMOS process contributes minimal self-heating at 5 V, so thermal rise is dominated by package thermal resistance to ambient, typically well under 1 W even at full toggle activity. Always provide adequate PCB copper area for socketed ceramic packages.
When migrating the EP1810JC-35 footprint to the EP1810GC-35 (Gull-Wing) variant, the PCB land pattern is identical at 68 pads, but the lead-form differs: JC uses J-bend for through-hole/socket assembly while GC uses Gull-Wing for surface-mount soldering. According to Altera package drawings, both share a 1.27 mm pad pitch. Verify your PCB land pattern matches the IPC-7351 standard for CQCC-68 before switching lead-form, especially for high-vibration or thermal-cycling applications where Gull-Wing provides better solder-joint reliability.
Estimated: the EP1810JC-35's 5 V CMOS output drive is rated for typical TTL load compatibility (e.g. 4 mA IOL / -4 mA IOH per Altera datasheet). When driving long backplane traces or high-capacitive loads, add series-damping resistors near the output pins to control overshoot and ringing. For buses longer than 200 mm, use 33 ohm series resistors to match the typical 50-70 ohm trace impedance; for shorter board-internal traces, no series termination is required. The 35 ns propagation delay budget includes typical output rise/fall times of 3-5 ns at 50 pF load.
Compliance Information
RoHS compliant and lead-free per Altera-Price distributor listing. REACH, halogen-free, and conflict-minerals status not explicitly listed in the verified web data and marked unknown. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC. For automotive or industrial applications, consider MAX V CPLD family with explicit automotive qualification.
