EP1810GI-45 vs EP1810JC-35 Comparison
Detailed side-by-side comparison of EP1810GI-45 by Altera and EP1810JC-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810GI-45 | EP1810JC-35 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $56.40 | $5.48 |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | — |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | 35 ns (max) |
| Speed Grade | -45 | — |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Pin Count | 68 | — |
| Mounting Type | Through-Hole | Surface Mount (J-Lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS Status | Non-compliant (ceramic PGA) | Compliant (per Altera listing) |
| Lead-Free | No | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| Supply Voltage | [DATA_NEEDED: VCC range] | — |
| Device Family | — | Classic EPLD (EP1810) |
| Number of Macrocells | — | 48 |
| Maximum Clock Frequency | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| Operating Temperature Range | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |