EP1810GI-45 vs EP1810JC-35 对比
详细并排对比 EP1810GI-45 出自 Altera 和 EP1810JC-35 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810GI-45 | EP1810JC-35 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $56.40 | $5.48 |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | — |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | 35 ns (max) |
| Speed Grade | -45 | — |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| 引脚数量 | 68 | — |
| 安装类型 | Through-Hole | Surface Mount (J-Lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS 状态 | Non-compliant (ceramic PGA) | Compliant (per Altera listing) |
| Lead-Free | No | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | — |
| 电源电压 | [DATA_NEEDED: VCC range] | — |
| Device Family | — | Classic EPLD (EP1810) |
| Number of Macrocells | — | 48 |
| 最大时钟频率 | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| 工作温度范围 | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |