EP1810JC-25 vs EP1810JC-45 Comparison
Detailed side-by-side comparison of EP1810JC-25 by Intel and EP1810JC-45 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810JC-25 | EP1810JC-45 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.80 | $21.10 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera/Intel Classic EPLD (EP1810 series) | EP1810 (Classic EPLD Family) |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Operating Temperature | -40 °C to 85 °C (industrial, per distributor listings) | — |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS, UV-erasable |
| Package | 28-pin ceramic DIP (J) with quartz window | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Mounting Type | Through-hole | Surface Mount |
| Erasure Method | UV light (windowed package) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Lifecycle Status | NRND (Not Recommended for New Designs) | — |
| Equivalent Gates | — | 2100 gates |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Clock Frequency | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Pin Count | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |