EP1810JC-25 vs EP1810JC-45 Comparación
Comparación detallada lado a lado de EP1810JC-25 por Intel y EP1810JC-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-25 | EP1810JC-45 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,80 | $21,10 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera/Intel Classic EPLD (EP1810 series) | EP1810 (Classic EPLD Family) |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperatura de funcionamiento | -40 °C to 85 °C (industrial, per distributor listings) | — |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS, UV-erasable |
| Encapsulado | 28-pin ceramic DIP (J) with quartz window | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Tipo de montaje | Through-hole | Surface Mount |
| Erasure Method | UV light (windowed package) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Estado del ciclo de vida | NRND (Not Recommended for New Designs) | — |
| Equivalent Gates | — | 2100 gates |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Frecuencia de reloj máxima | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Recuento de pines | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |