EP1810JC-35 vs EP1810GI-45 Comparison
Detailed side-by-side comparison of EP1810JC-35 by Intel and EP1810GI-45 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810JC-35 | EP1810GI-45 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.48 | $56.40 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | UV Erasable Programmable Logic Device (EPLD) |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns |
| Maximum Clock Frequency | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | Ceramic Pin Grid Array with UV window |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Operating Temperature Range | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS Status | Compliant (per Altera listing) | Non-compliant (ceramic PGA) |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Mounting Type | Surface Mount (J-Lead) | Through-Hole |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 24 |
| Flip-Flops | — | 48 |
| Speed Grade | — | -45 |
| Technology | — | CMOS |
| Pin Count | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| Supply Voltage | — | [DATA_NEEDED: VCC range] |