EP1810JC-35 vs EP1810JM-45 Comparison

Detailed side-by-side comparison of EP1810JC-35 by Intel and EP1810JM-45 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810JC-35 EP1810JM-45
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.48 $14.20
Device Family Classic EPLD (EP1810) Classic EPLD (EP1810 series)
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) —
Number of Macrocells 48 —
Propagation Delay (tpd) 35 ns (max) 45 ns (max, -45 speed grade)
Maximum Clock Frequency [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS —
Supply Voltage (Vcc) 5 V (nominal) —
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) JLCC-68 (ceramic J-leaded chip carrier)
Number of Terminals 68 —
Terminal Form J-Bend —
Operating Temperature Range 0°C to 70°C (Commercial) —
Temperature Grade Commercial —
Erasure Method UV (quartz-windowed ceramic package) —
RoHS Status Compliant (per Altera listing) [DATA_NEEDED: RoHS status - legacy mil-spec part]
Lead-Free Status Lead-free (per distributor listing) —
Mounting Type Surface Mount (J-Lead) Surface Mount (J-lead)
Logic Architecture Programmable AND/OR array with macrocell outputs —
Macrocells — 48
Usable Gates — ~900 gates
Supply Voltage (VCC) — 4.5 V to 5.5 V
Technology — CMOS, UV-EPROM configuration
Package Code — JM (windowed ceramic, UV-erasable)
Pin Count — 68
Operating Temperature — -55 C to +125 C (military grade)
I/O Compatibility — CMOS / TTL
Configuration Method — JEDEC fuse map, EPROM programmer
Programming Technology — UV-erasable EPROM (non-volatile, instant-on)
Logic Type — EPLD / PLD (programmable logic device)
MSL Level — [DATA_NEEDED: MSL level]

Datasheets & Resources

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