EP1810JC-35 vs EP1810JM-45 비교
다음의 상세 나란히 비교: EP1810JC-35 제조: Intel 및 EP1810JM-45 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC-35 | EP1810JM-45 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $5.48 | $14.20 |
| Device Family | Classic EPLD (EP1810) | Classic EPLD (EP1810 series) |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns (max, -45 speed grade) |
| 최대 클록 주파수 | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | JLCC-68 (ceramic J-leaded chip carrier) |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| 동작 온도 범위 | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS 상태 | Compliant (per Altera listing) | [DATA_NEEDED: RoHS status - legacy mil-spec part] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| 실장 유형 | Surface Mount (J-Lead) | Surface Mount (J-lead) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Macrocells | — | 48 |
| Usable Gates | — | ~900 gates |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-EPROM configuration |
| Package Code | — | JM (windowed ceramic, UV-erasable) |
| 핀 수 | — | 68 |
| 동작 온도 | — | -55 C to +125 C (military grade) |
| I/O Compatibility | — | CMOS / TTL |
| Configuration Method | — | JEDEC fuse map, EPROM programmer |
| Programming Technology | — | UV-erasable EPROM (non-volatile, instant-on) |
| Logic Type | — | EPLD / PLD (programmable logic device) |
| MSL 레벨 | — | [DATA_NEEDED: MSL level] |