EP1810JC-35 vs EP1810JM-45 Comparación
Comparación detallada lado a lado de EP1810JC-35 por Intel y EP1810JM-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-35 | EP1810JM-45 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,48 | $14,20 |
| Device Family | Classic EPLD (EP1810) | Classic EPLD (EP1810 series) |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns (max, -45 speed grade) |
| Frecuencia de reloj máxima | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | JLCC-68 (ceramic J-leaded chip carrier) |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Rango de temperatura de funcionamiento | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| Estado RoHS | Compliant (per Altera listing) | [DATA_NEEDED: RoHS status - legacy mil-spec part] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Tipo de montaje | Surface Mount (J-Lead) | Surface Mount (J-lead) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Macrocells | — | 48 |
| Usable Gates | — | ~900 gates |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-EPROM configuration |
| Package Code | — | JM (windowed ceramic, UV-erasable) |
| Recuento de pines | — | 68 |
| Temperatura de funcionamiento | — | -55 C to +125 C (military grade) |
| I/O Compatibility | — | CMOS / TTL |
| Configuration Method | — | JEDEC fuse map, EPROM programmer |
| Programming Technology | — | UV-erasable EPROM (non-volatile, instant-on) |
| Logic Type | — | EPLD / PLD (programmable logic device) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |