EP1810LC-25 vs EP1810LC-20 Comparison
Detailed side-by-side comparison of EP1810LC-25 by Altera and EP1810LC-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810LC-25 | EP1810LC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $7.85 |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Package | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC |
| Package Code | LC = 68-pin JLCC | — |
| Mounting Type | Surface Mount | Surface Mount |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS EPROM |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| Lifecycle Status | Obsolete (legacy Altera Classic family) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED: rohs status] |
| Operating Temperature | [DATA_NEEDED: temperature grade for LC package] | 0C to +70C (commercial) |
| Family | — | Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Maximum Operating Frequency | — | 50 MHz |
| Supply Voltage | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-Erasable / OTP |
| Package Suffix | — | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | — | 20 ns (commercial) |